Re: [RFC] uartlite driver MicroBlaze compatability

[John Williams <jwilliams@itee.uq.edu.au>]

Hi Peter,

Peter Korsgaard wrote:

> JW> The attached patch gets your uartlite driver going on MicroBlaze.
> 
> Nice!
> 
> JW> All readb/writeb ops are converted to ioread32/iowrite32.
> 
> JW> On MicroBlaze readb/writeb are picking up the MSB, instead of LSB,
> JW> and thus reading all zeros instead of the 8-bit
> JW> control/status/FIFO registers that you intended.
> 
> I take it that the microblaze is big endian? Then you just need to add
> 3 to the base address and everything should work without your patch.

I struggle to see adding 3 to the base address in the platform driver as 
a clean solution.  The base address of the peripheral is 0x10240000, or 
whatever, not 0x10240003.

I understand the reasoning for it, but from the platform's perspective 
it seems wrong.

If you read the opb_uartlite datasheet, it says that bits 0-26 of the 
FIFO, CTRL and STATUS regs are "reserved".  It doesn't say, this is an 
8-bit peripheral that is mapped onto a 32bit bus with a stride of 4.

If you also read page 6 , under address map, it says

BASE_ADDRESS+0 : read from receive FIFO
BASE_ADDRESS+4 : write to transmit FIFO
and so on.

It is a 32-bit peripheral, it just so happens the 24 of those bits are 
currently "reserved".

Grant's recanting may have been triggered by the figure on page 4 of the 
datasheet, which is generic Xilnx IP Core datasheet material explaining 
the endian interpretation for different data widths.

> JW> Can you please confirm if this works on PPC?
> 
> It won't as ioread/write does big/little endian byte swapping. Isn't
> that done on microblaze?

Not presently, but I will fix that.

I think that's Grant's approach of using in/out_be32, and the real base 
address (ie not +3) is the only logically correct solution.

Regards,

John