Re: PCI target implementation on AMCC PPC CPUs

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Leonid,

In case they are not in the document:

There are several fundamental problems with the AMCC 440EP
acting as a PCI target/slave;

1. As a PCI target, there is only one way to generate
    an interrupt to a host; you basically toggle the
    interrupt pin. This makes it tricky to develop a
    host-to-slave communications protocol, eg. its
    hard to use the single interrupt to indicate various
    interrupt states, eg. target-to-host buffer has
    data versus host-to-target buffer has been emptied.
    Ideally AMCC should have implemented mailboxes and/or
    doorbell registers like any other sane PCI target
    device (eg. some the Freescale processors, or any of
    the PLX technologies chips).

2. Look in the data sheet and see if you can figure out
    how the host processor can generate an interrupt to
    the PowerPC core ... oops, you can't. That kind of
    makes it difficult to work with doesn't it.

    A work around would be to have the host write to the
    GPIO register and wire a GPIO pin back to an external
    interrupt pin. Then you would not be able to use any
    other GPIO pin in that GPIO register since there is
    no way to arbitrate host access versus PowerPC core
    access.

This was the other reason I ditched the AMCC part in
favor of the Freescale part.

If you are looking at other parts, make sure you look
in the PCI configuration space of the processor reference
manual. Many processors have the interrupt pin register
hardwired to zero, i.e., they can not be used as target
devices, only hosts. In that case you'd have to add an
intel 21555 non-transparent bridge to make the device
a target.

Cheers,
Dave