From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from buildserver.ru.mvista.com (unknown [85.21.88.6]) by ozlabs.org (Postfix) with ESMTP id 0F134DDFD5 for ; Fri, 21 Sep 2007 04:47:25 +1000 (EST) Message-ID: <46F2BFFA.1060203@ru.mvista.com> Date: Thu, 20 Sep 2007 22:46:18 +0400 From: Valentine Barshak MIME-Version: 1.0 To: linuxppc-dev@ozlabs.org Subject: Re: [PATCH 2/2] PowerPC: Fix Sequoia MAL0 and EMAC dts entries. References: <20070918172510.GA30944@ru.mvista.com> <20070918172913.GA31098@ru.mvista.com> <20070919010526.GA23646@localhost.localdomain> <46F10478.1080506@ru.mvista.com> In-Reply-To: <46F10478.1080506@ru.mvista.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Cc: David Gibson List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Valentine Barshak wrote: > David Gibson wrote: >> On Tue, Sep 18, 2007 at 09:29:13PM +0400, Valentine Barshak wrote: >>> According to PowerPC 440EPx documentation, >>> MAL0 is comprised of four channels (two transmit and two receive). >>> Each channel is dedicated to one of two EMAC cores. >>> This patch fixes Sequoia DTS MAL0 entry and EMAC entries, >>> assigning correct channel numbers to EMACs. >> >> Hrm.. did they change the EMAC in 440EPx to only use one MAL >> tx-channel? All the older ones could use two (for no readily apparent >> reason, IMO). >> > Yes, they did. > Just 1 tx and 1 rx-channel per EMAC. Just 2 bits to select channels, > while all other bits in MAL registers are reserved. > I'm not sure why they did it (possible bus bandwidth problems), but it's > impossible to set more than 1 rx/tx channel for each EMAC in 440EPx. Josh, David, is this patch OK?