From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.semihalf.com (mail.semihalf.com [83.12.36.68]) by ozlabs.org (Postfix) with ESMTP id 1576DDDECA for ; Sun, 7 Oct 2007 21:21:06 +1000 (EST) Received: from localhost (unknown [127.0.0.1]) by mail.semihalf.com (Postfix) with ESMTP id 735D6143DA for ; Sun, 7 Oct 2007 13:21:04 +0200 (CEST) Received: from mail.semihalf.com ([127.0.0.1]) by localhost (mail.semihalf.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 14326-10 for ; Sun, 7 Oct 2007 13:21:02 +0200 (CEST) Message-ID: <4708C112.9020506@semihalf.com> Date: Sun, 07 Oct 2007 13:20:50 +0200 From: Marian Balakowicz MIME-Version: 1.0 To: linuxppc-dev@ozlabs.org Subject: [PATCH 04/15] [POWERPC] CM5200 DTS References: <47075FA7.3030108@semihalf.com> In-Reply-To: <47075FA7.3030108@semihalf.com> Content-Type: text/plain; charset=ISO-8859-2 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Add device tree source file for CM5200 board. Signed-off-by Marian Balakowicz Signed-off-by: Jan Wrobel --- cm5200.dts | 284 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 284 insertions(+) diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts new file mode 100644 index 0000000..96d2ee4 --- /dev/null +++ b/arch/powerpc/boot/dts/cm5200.dts @@ -0,0 +1,284 @@ +/* + * CM5200 board Device Tree Source + * + * Copyright (C) 2007 Semihalf + * Modified for CM5200 by Jan Wrobel + * + * Copyright 2006-2007 Secret Lab Technologies Ltd. + * Grant Likely + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * WARNING: Do not depend on this tree layout remaining static just yet. + * The MPC5200 device tree conventions are still in flux + * Keep an eye on the linuxppc-dev mailing list for more details + */ + +/ { + model = "cm5200"; + compatible = "fsl,cm5200\0generic-mpc5200"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,5200@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; + i-cache-line-size = <20>; + d-cache-size = <4000>; // L1, 16K + i-cache-size = <4000>; // L1, 16K + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + 32-bit; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 04000000>; // 64MB + }; + + soc5200@f0000000 { + model = "fsl,mpc5200b"; + compatible = "mpc5200"; + revision = ""; // from bootloader + #interrupt-cells = <3>; + device_type = "soc"; + ranges = <0 f0000000 f0010000>; + reg = ; + bus-frequency = <0>; // from bootloader + system-frequency = <0>; // from bootloader + + cdm@200 { + compatible = "mpc5200b-cdm\0mpc5200-cdm"; + reg = <200 38>; + }; + + mpc5200_pic: pic@500 { + // 5200 interrupts are encoded into two levels; + interrupt-controller; + #interrupt-cells = <3>; + device_type = "interrupt-controller"; + compatible = "mpc5200b-pic\0mpc5200-pic"; + reg = <500 80>; + built-in; + }; + + gpt@600 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <0>; + reg = <600 10>; + interrupts = <1 9 0>; + interrupt-parent = <&mpc5200_pic>; + has-wdt; + }; + + gpt@610 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <1>; + reg = <610 10>; + interrupts = <1 a 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpt@620 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <2>; + reg = <620 10>; + interrupts = <1 b 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpt@630 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <3>; + reg = <630 10>; + interrupts = <1 c 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpt@640 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <4>; + reg = <640 10>; + interrupts = <1 d 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpt@650 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <5>; + reg = <650 10>; + interrupts = <1 e 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpt@660 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <6>; + reg = <660 10>; + interrupts = <1 f 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpt@670 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc5200-gpt"; + device_type = "gpt"; + cell-index = <7>; + reg = <670 10>; + interrupts = <1 10 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + rtc@800 { // Real time clock + compatible = "mpc5200b-rtc\0mpc5200-rtc"; + device_type = "rtc"; + reg = <800 100>; + interrupts = <1 5 0 1 6 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpio@b00 { + compatible = "mpc5200b-gpio\0mpc5200-gpio"; + reg = ; + interrupts = <1 7 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpio-wkup@c00 { + compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup"; + reg = ; + interrupts = <1 8 0 0 3 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + spi@f00 { + device_type = "spi"; + compatible = "mpc5200b-spi\0mpc5200-spi"; + reg = ; + interrupts = <2 d 0 2 e 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + usb@1000 { + device_type = "usb-ohci-be"; + compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be"; + reg = <1000 ff>; + interrupts = <2 6 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + bestcomm@1200 { + device_type = "dma-controller"; + compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm"; + reg = <1200 80>; + interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 + 3 4 0 3 5 0 3 6 0 3 7 0 + 3 8 0 3 9 0 3 a 0 3 b 0 + 3 c 0 3 d 0 3 e 0 3 f 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + xlb@1f00 { + compatible = "mpc5200b-xlb\0mpc5200-xlb"; + reg = <1f00 100>; + }; + + serial@2000 { // PSC1 + device_type = "serial"; + compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart"; + port-number = <0>; // Logical port assignment + cell-index = <0>; + reg = <2000 100>; + interrupts = <2 1 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + serial@2200 { // PSC2 + device_type = "serial"; + compatible = "mpc5200-psc-uart"; + port-number = <1>; // Logical port assignment + cell-index = <1>; + reg = <2200 100>; + interrupts = <2 2 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + serial@2400 { // PSC3 + device_type = "serial"; + compatible = "mpc5200-psc-uart"; + port-number = <2>; // Logical port assignment + cell-index = <2>; + reg = <2400 100>; + interrupts = <2 3 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + serial@2c00 { // PSC6 + device_type = "serial"; + compatible = "mpc5200-psc-uart"; + port-number = <5>; // Logical port assignment + cell-index = <5>; + reg = <2c00 100>; + interrupts = <2 4 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + ethernet@3000 { + device_type = "network"; + compatible = "mpc5200b-fec\0mpc5200-fec"; + reg = <3000 800>; + interrupts = <2 5 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + i2c@3d40 { + device_type = "i2c"; + compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c"; + cell-index = <1>; + reg = <3d40 40>; + interrupts = <2 10 0>; + interrupt-parent = <&mpc5200_pic>; + fsl5200-clocking; + }; + + sram@8000 { + device_type = "sram"; + compatible = "mpc5200b-sram\0mpc5200-sram\0sram"; + reg = <8000 4000>; + }; + + flash@c000000 { + device_type = "rom"; + compatible = "direct-mapped"; + reg = <0c000000 02000000>; + probe-type = "CFI"; + bank-width = <2>; + partitions = <00000000 00060000 + 00060000 00020000 + 00080000 00020000 + 000a0000 00020000 + 000c0000 00200000 + 002c0000 01b40000 + 01e00000 00200000>; + partition-names = "uboot\0env\0redund_env\0dtb\0kernel\0rootfs\0config"; + }; + }; +};