Re: mmap + segfaults on MPC8349E

[David Hawkins <dwh@ovro.caltech.edu>]

Hi,

You haven't really provided enough information.

> We wrote some simple drivers/modules to mmap() FPGA registers to user space.
> At the moment, for testing, we reserve the upper x-MB of RAM, and mmap() 
> there, instead.

1. The FPGA is located where? The local bus, or the PCI bus?
    What frequency are you trying to operate at?

2. If its on the local bus, do you access it using GPCM or UPM?
    Have you setup either correctly?
    Have you confirmed the bus timing with a logic analyzer?

3. Have you created a bus functional model of the processor bus
    that you have then run with your FPGA bus in ModelSim to
    confirm that your FPGA performs correctly.

4. Have you tried burst and non-burst access by either using
    DMA, or treating the memory area as cacheable or non-cacheable?
    Have you checked those cases with simulation and then
    with a scope or logic analyzer?

5. Did you try running stand-alone tests in U-Boot, to go for a
    more bare-metal debug approach?

No point in debugging software if you have no idea whether the
hardware behaves. So confirm that you have tested your hardware
first.

My board design uses the MPC8349EA, I have an Altera Stratix II
FPGA on the local bus. I use GPCM to access flash on the local
bus via the FPGA, and UPM to access FPGA registers. I don't
have boards yet, but I've got a pretty good handle on how the
interface should work.

Cheers,
Dave