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Date: Thu, 17 Apr 2008 15:14:23 -0500
From: Scott Wood <scottwood@freescale.com>
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To: Timur Tabi <timur@freescale.com>
Subject: Re: [PATCH 2/5] [POWERPC] QE: add support for QE USB clocks routing
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Timur Tabi wrote:
> Scott Wood wrote:
> 
>> No.  clrsetbits operates on I/O registers, not RAM.
> 
> Does lwarx require the EA to be cached memory or something?

That's implementation dependent, and support for accesses to uncached 
memory is being phased out of book E according to the E500 manual.

>  The reservation is held within the processor, so it should work on I/O.

Even if the core supports lwarx/stwcx to uncached memory, the I/O bus 
must support atomic read-modify-write transactions for this to work.

Why do you think you need lwarx/stwcx to I/O?

-Scott