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Date: Fri, 30 May 2008 15:36:50 -0500
From: Scott Wood <scottwood@freescale.com>
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To: Kim Phillips <kim.phillips@freescale.com>
Subject: Re: [PATCH 2/2] talitos: Freescale integrated security engine (SEC)
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Cc: Evgeniy Polyakov <johnpol@2ka.mipt.ru>, linuxppc-dev@ozlabs.org,
	mr.scada@gmail.com, linux-crypto@vger.kernel.org,
	herbert@gondor.apana.org.au
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Kim Phillips wrote:
> On Fri, 30 May 2008 15:19:43 -0500
> Scott Wood <scottwood@freescale.com> wrote:
> 
>> Kim Phillips wrote:
>>> On Fri, 30 May 2008 14:41:17 -0500
>>> Scott Wood <scottwood@freescale.com> wrote:
>>>
>>>> Kim Phillips wrote:
>>>>> On Fri, 30 May 2008 22:09:04 +0400
>>>>> Evgeniy Polyakov <johnpol@2ka.mipt.ru> wrote:
>>>>>> Don't you want to protect against simultaneous access to register space
>>>>>> from different CPUs? Or it is single processor board only?
>>>>> Doesn't linux mask the IRQ line for the interrupt currently being
>>>>> serviced, and on all processors?
>>>> Yes.  Could there be interference from non-interrupt driver code on 
>>>> another cpu (or interrupted code), though?
>>> not that I can see - the fetch fifo register writes are protected with
>>> per-channel spinlocks.
>> But you don't take the spinlocks from the interrupt handler.
> 
> why can't fetch fifo registers be written the same time the ISR is
> being accessed?

I don't know -- you brought them up.  My question was whether there's 
anything that the ISR touches that is also touched by non-ISR code.

-Scott