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Message-ID: <4872DC9C.4000706@us.ibm.com>
Date: Mon, 07 Jul 2008 20:18:52 -0700
From: Mike Mason <mmlnx@us.ibm.com>
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To: paulus@samba.org, benh@kernel.crashing.org, linasvepstas@gmail.com,
	linuxppc-dev@ozlabs.org
Subject: [PATCH] Restore PERR/SERR bit settings during EEH device recovery
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The following patch restores the PERR and SERR bits in the PCI
command register during an EEH device recovery.
We have found at least one case (an Agilent test card) where the
PERR/SERR bits are set to 1 by firmware at boot time, but are
not restored to 1 during EEH recovery.  The patch fixes the
Agilent card problem.  It has been tested on several other 
EEH-enabled cards with no regressions.

Signed-off-by: Mike Mason <mmlnx@us.ibm.com>

--- linux-2.6.26-rc9/arch/powerpc/platforms/pseries/eeh.c	2008-07-07 16:06:57.000000000 -0700
+++ linux-2.6.26-rc9-new/arch/powerpc/platforms/pseries/eeh.c	2008-07-07 16:11:10.000000000 -0700
@@ -812,6 +812,7 @@
 static inline void __restore_bars (struct pci_dn *pdn)
 {
 	int i;
+	u32 cmd;
 
 	if (NULL==pdn->phb) return;
 	for (i=4; i<10; i++) {
@@ -832,6 +833,15 @@
 
 	/* max latency, min grant, interrupt pin and line */
 	rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
+
+	/* Restore PERR & SERR bits, some devices require it,
+	   don't touch the other command bits */
+	rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+	if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+		cmd |= PCI_COMMAND_PARITY;
+	if (pdn->config_space[1] & PCI_COMMAND_SERR)
+		cmd |= PCI_COMMAND_SERR;
+	rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
 }
 
 /**