Re: [PATCH] powerpc: i2c-mpc: make speed registers configurable via FDT

[Timur Tabi <timur@freescale.com>]

Grant Likely wrote:

> This is a solved problem.  The device tree simple claims compatibility
> with an older part that has the identical register-level interface.

That would assume that the clock frequency is the only thing that decides
compatibility, which may technically be true now, but I don't think it's a good
idea.

I don't understand what's wrong with simply specifying the actual clock
frequency that the device uses?  It varies from SOC to SOC, but U-Boot
calculates today already:

#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
	gd->i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->i2c1_clk = sys_info.freqSystemBus / 3;
	else
		gd->i2c1_clk = sys_info.freqSystemBus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->i2c1_clk = sys_info.freqSystemBus / 2;
#endif
	gd->i2c2_clk = gd->i2c1_clk;

We need this ugliness in U-Boot.  Let's take advantage of this and do something
clean and elegant in the device tree.

-- 
Timur Tabi
Linux kernel developer at Freescale