Device tree question

Device tree question

[Steven A. Falco]

I have added a compact flash to the external bus of a Sequoia
(PPC440EPx) evaluation board.  It is wired to CS1, and U-boot is set to
configure CS1 to be at address 0xc1000000.  U-boot can access the
device, and reports the correct partition table, etc. so I believe the
hardware is ok.

I've created a device-tree entry under the EBC0 section of the
sequoia.dts file:

                pata@1,0 {
                    compatible = "harris,hydra_temp-pata", "ata-generic";
                    bank-width = <2>;
                    reg = <1 0 20 1 80 20>;
                    reg-shift = <4>;
                    pio-mode = <4>;
                    interrupts = <27 4>;
                    interrupt-parent = <&UIC0>;
                };
            };

This seems to be correct, because if I turn on debug in prom_parse, I
see a translation that looks reasonable:

OF: translating address: 00000001 00000000
OF: parent bus is default (na=1, ns=1) on /plb/opb
OF: walking ranges...
OF: default map, cp=0, s=4000000, da=100000000
OF: default map, cp=100000000, s=100000, da=100000000
OF: parent translation for: c1000000
OF: with offset: 0
OF: one level translation: c1000000
OF: parent bus is default (na=2, ns=1) on /plb
OF: walking ranges...
OF: default map, cp=0, s=80000000, da=c1000000
OF: default map, cp=80000000, s=80000000, da=c1000000
OF: parent translation for: 00000001 80000000
OF: with offset: 41000000
OF: one level translation: 00000001 c1000000
OF: parent bus is default (na=2, ns=1) on /
OF: no ranges, 1:1 translation
OF: parent translation for: 00000000 00000000
OF: with offset: 1c1000000
OF: one level translation: 00000001 c1000000
OF: reached root node
OF: ** translation for device /plb/opb/ebc/pata@1,0 **
OF: bus is default (na=2, ns=1) on /plb/opb/ebc

(There is another translation for the alternate registers but I'll omit
it for brevity.)

However, there is something wrong, because I get an oops:

Machine check in kernel mode.
Data Write PLB Error
Oops: Machine check, sig: 7 [#1]
LTT NESTING LEVEL : 0
Hydra_temp
Modules linked in:
NIP: c01e4618 LR: c01e4608 CTR: c01e4078
REGS: c0398f50 TRAP: 0214   Not tainted  (2.6.25.4-00021-g4b3b5ea-dirty)
MSR: 00029000 <EE,ME>  CR: 24044028  XER: 20000007
TASK = cf808400[1] 'swapper' THREAD: cf826000
GPR00: 00000008 cf827ce0 cf808400 cf3ac000 d1078080 00000000 00000001
c03869c0
GPR08: 00000000 c01e4078 cf3ac000 00000001 24044022 00000000 c02e977c
c02e97e0
GPR16: c02e97c8 c036a8bc c02e97f4 c02e9808 c037c0a8 c0386978 00000000
cf360190
GPR24: 00000027 c0386a64 00000000 00000000 cf360190 00000000 cf360194
cf3ac000
NIP [c01e4618] ata_bmdma_freeze+0x44/0x70
LR [c01e4608] ata_bmdma_freeze+0x34/0x70
Call Trace:
[cf827ce0] [0000001f] 0x1f (unreliable)
[cf827cf0] [c01e4c14] __ata_port_freeze+0x3c/0x5c
[cf827d00] [c01e4fa4] ata_eh_freeze_port+0x40/0x5c
[cf827d20] [c01d6868] ata_host_start+0xd8/0x208
[cf827d40] [c01dd2f4] ata_host_activate+0x28/0x124
[cf827d70] [c02a60c4] 0xc02a60c4
[cf827db0] [c02a642c] 0xc02a642c
[cf827e50] [c0222a7c] of_platform_device_probe+0x5c/0x560
[cf827e70] [c01b3148] driver_probe_device+0xb8/0x1e8
[cf827e90] [c01b3470] __driver_attach+0xcc/0xf8
[cf827eb0] [c01b21c4] bus_for_each_dev+0x5c/0x98
[cf827ee0] [c01b2f50] driver_attach+0x24/0x34
[cf827ef0] [c01b2da8] bus_add_driver+0x1d8/0x258
[cf827f20] [c01b371c] driver_register+0x48/0x114
[cf827f40] [c0222950] of_register_driver+0x54/0x70
[cf827f50] [c035ed08] pata_of_platform_init+0x20/0x30
[cf827f60] [c03471cc] kernel_init+0xc8/0x2ac
[cf827ff0] [c000e44c] original_kernel_thread+0x44/0x60

My question is: Did I do the device-tree entry incorrectly or is
something else wrong?  I'll keep trying to figure it out on my own, but
if anyone has any tips on debugging this, I'd love to hear them.

    Steve

Re: Device tree question

[Benjamin Herrenschmidt]

On Thu, 2008-08-07 at 15:56 -0400, Steven A. Falco wrote:
> I have added a compact flash to the external bus of a Sequoia
> (PPC440EPx) evaluation board.  It is wired to CS1, and U-boot is set to
> configure CS1 to be at address 0xc1000000.  U-boot can access the
> device, and reports the correct partition table, etc. so I believe the
> hardware is ok.
> 
> I've created a device-tree entry under the EBC0 section of the
> sequoia.dts file:
> 
>                 pata@1,0 {
>                     compatible = "harris,hydra_temp-pata", "ata-generic";
>                     bank-width = <2>;
>                     reg = <1 0 20 1 80 20>;
>                     reg-shift = <4>;
>                     pio-mode = <4>;
>                     interrupts = <27 4>;
>                     interrupt-parent = <&UIC0>;
>                 };
>             };
> 
> This seems to be correct, because if I turn on debug in prom_parse, I
> see a translation that looks reasonable:

Did you check that the resulting physical address was indeed where you
device is supposed to be addressed ?

Ben.

> OF: translating address: 00000001 00000000
> OF: parent bus is default (na=1, ns=1) on /plb/opb
> OF: walking ranges...
> OF: default map, cp=0, s=4000000, da=100000000
> OF: default map, cp=100000000, s=100000, da=100000000
> OF: parent translation for: c1000000
> OF: with offset: 0
> OF: one level translation: c1000000
> OF: parent bus is default (na=2, ns=1) on /plb
> OF: walking ranges...
> OF: default map, cp=0, s=80000000, da=c1000000
> OF: default map, cp=80000000, s=80000000, da=c1000000
> OF: parent translation for: 00000001 80000000
> OF: with offset: 41000000
> OF: one level translation: 00000001 c1000000
> OF: parent bus is default (na=2, ns=1) on /
> OF: no ranges, 1:1 translation
> OF: parent translation for: 00000000 00000000
> OF: with offset: 1c1000000
> OF: one level translation: 00000001 c1000000
> OF: reached root node
> OF: ** translation for device /plb/opb/ebc/pata@1,0 **
> OF: bus is default (na=2, ns=1) on /plb/opb/ebc
> 
> (There is another translation for the alternate registers but I'll omit
> it for brevity.)
> 
> However, there is something wrong, because I get an oops:
> 
> Machine check in kernel mode.
> Data Write PLB Error
> Oops: Machine check, sig: 7 [#1]
> LTT NESTING LEVEL : 0
> Hydra_temp
> Modules linked in:
> NIP: c01e4618 LR: c01e4608 CTR: c01e4078
> REGS: c0398f50 TRAP: 0214   Not tainted  (2.6.25.4-00021-g4b3b5ea-dirty)
> MSR: 00029000 <EE,ME>  CR: 24044028  XER: 20000007
> TASK = cf808400[1] 'swapper' THREAD: cf826000
> GPR00: 00000008 cf827ce0 cf808400 cf3ac000 d1078080 00000000 00000001
> c03869c0
> GPR08: 00000000 c01e4078 cf3ac000 00000001 24044022 00000000 c02e977c
> c02e97e0
> GPR16: c02e97c8 c036a8bc c02e97f4 c02e9808 c037c0a8 c0386978 00000000
> cf360190
> GPR24: 00000027 c0386a64 00000000 00000000 cf360190 00000000 cf360194
> cf3ac000
> NIP [c01e4618] ata_bmdma_freeze+0x44/0x70
> LR [c01e4608] ata_bmdma_freeze+0x34/0x70
> Call Trace:
> [cf827ce0] [0000001f] 0x1f (unreliable)
> [cf827cf0] [c01e4c14] __ata_port_freeze+0x3c/0x5c
> [cf827d00] [c01e4fa4] ata_eh_freeze_port+0x40/0x5c
> [cf827d20] [c01d6868] ata_host_start+0xd8/0x208
> [cf827d40] [c01dd2f4] ata_host_activate+0x28/0x124
> [cf827d70] [c02a60c4] 0xc02a60c4
> [cf827db0] [c02a642c] 0xc02a642c
> [cf827e50] [c0222a7c] of_platform_device_probe+0x5c/0x560
> [cf827e70] [c01b3148] driver_probe_device+0xb8/0x1e8
> [cf827e90] [c01b3470] __driver_attach+0xcc/0xf8
> [cf827eb0] [c01b21c4] bus_for_each_dev+0x5c/0x98
> [cf827ee0] [c01b2f50] driver_attach+0x24/0x34
> [cf827ef0] [c01b2da8] bus_add_driver+0x1d8/0x258
> [cf827f20] [c01b371c] driver_register+0x48/0x114
> [cf827f40] [c0222950] of_register_driver+0x54/0x70
> [cf827f50] [c035ed08] pata_of_platform_init+0x20/0x30
> [cf827f60] [c03471cc] kernel_init+0xc8/0x2ac
> [cf827ff0] [c000e44c] original_kernel_thread+0x44/0x60
> 
> My question is: Did I do the device-tree entry incorrectly or is
> something else wrong?  I'll keep trying to figure it out on my own, but
> if anyone has any tips on debugging this, I'd love to hear them.
> 
>     Steve
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev

Re: Device tree question

[Steven A. Falco]

[-- Attachment #1: Type: text/plain, Size: 1507 bytes --]

Benjamin Herrenschmidt wrote:
> On Thu, 2008-08-07 at 15:56 -0400, Steven A. Falco wrote:
>   
>> I have added a compact flash to the external bus of a Sequoia
>> (PPC440EPx) evaluation board.  It is wired to CS1, and U-boot is set to
>> configure CS1 to be at address 0xc1000000.  U-boot can access the
>> device, and reports the correct partition table, etc. so I believe the
>> hardware is ok.
>>
>> I've created a device-tree entry under the EBC0 section of the
>> sequoia.dts file:
>>
>>                 pata@1,0 {
>>                     compatible = "harris,hydra_temp-pata", "ata-generic";
>>                     bank-width = <2>;
>>                     reg = <1 0 20 1 80 20>;
>>                     reg-shift = <4>;
>>                     pio-mode = <4>;
>>                     interrupts = <27 4>;
>>                     interrupt-parent = <&UIC0>;
>>                 };
>>             };
>>
>> This seems to be correct, because if I turn on debug in prom_parse, I
>> see a translation that looks reasonable:
>>     
>
> Did you check that the resulting physical address was indeed where you
> device is supposed to be addressed ?
>
> Ben
>   

They were wrong - I misinterpreted the reg-shift to be like the "stride"
used by u-boot.  But u-boot uses it as a multiplier, and reg-shift is
truly a shift.  So, I changed the shift to "2", and now the addresses
are correct.  I'm still having problems, but I'll start a new thread,
because the new problem concerns interrupts.

    Thanks,
    Steve


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device tree question

[Alan Bennett]

I want to make the mpc8272ads.dts tree work for my board.

I have an mpc8248
  128MB Flash@ f800_0000  (Spansion S29GL512N)
  128MB Flash@ D000_0000  (Spansion S29GL512N)
  BCSR@e400_0000
  2nd CSR@e410_0000
  RAM@e420_0000
  128MB SDRAM@[0x0..0800_0000]

Is it ok to have 0 in these:
	cpus {
		PowerPC,8272@0 {
         . . .
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
        . . .

How do I modify the following lines to match my hardware?

	localbus@f0010100 {
      . . .
		ranges = <0 0 fe000000 02000000
		          1 0 f4500000 00008000
		          3 0 f8200000 00008000>;

		flash@0,0 {
			compatible = "jedec-flash";
			reg = <0 0 2000000>;
			bank-width = <4>;
			device-width = <1>;
		};

		board-control@1,0 {
			reg = <1 0 20>;
			compatible = "fsl,mpc8272ads-bcsr";
		};
      . . .


====FULL MPC8278ads.dts

/*
 * MPC8272 ADS Device Tree Source
 *
 * Copyright 2005 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/ {
	model = "MPC8272ADS";
	compatible = "fsl,mpc8272ads";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8272@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <d#32>;
			i-cache-line-size = <d#32>;
			d-cache-size = <d#16384>;
			i-cache-size = <d#16384>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0 0>;
	};

	localbus@f0010100 {
		compatible = "fsl,mpc8272-localbus",
		             "fsl,pq2-localbus";
		#address-cells = <2>;
		#size-cells = <1>;
		reg = <f0010100 40>;

		ranges = <0 0 fe000000 02000000
		          1 0 f4500000 00008000
		          3 0 f8200000 00008000>;

		flash@0,0 {
			compatible = "jedec-flash";
			reg = <0 0 2000000>;
			bank-width = <4>;
			device-width = <1>;
		};

		board-control@1,0 {
			reg = <1 0 20>;
			compatible = "fsl,mpc8272ads-bcsr";
		};

		PCI_PIC: interrupt-controller@3,0 {
			compatible = "fsl,mpc8272ads-pci-pic",
			             "fsl,pq2ads-pci-pic";
			#interrupt-cells = <1>;
			interrupt-controller;
			reg = <3 0 8>;
			interrupt-parent = <&PIC>;
			interrupts = <14 8>;
		};
	};


	pci@f0010800 {
		device_type = "pci";
		reg = <f0010800 10c f00101ac 8 f00101c4 8>;
		compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		clock-frequency = <d#66666666>;
		interrupt-map-mask = <f800 0 0 7>;
		interrupt-map = <
		                 /* IDSEL 0x16 */
		                 b000 0 0 1 &PCI_PIC 0
		                 b000 0 0 2 &PCI_PIC 1
		                 b000 0 0 3 &PCI_PIC 2
		                 b000 0 0 4 &PCI_PIC 3

		                 /* IDSEL 0x17 */
		                 b800 0 0 1 &PCI_PIC 4
		                 b800 0 0 2 &PCI_PIC 5
		                 b800 0 0 3 &PCI_PIC 6
		                 b800 0 0 4 &PCI_PIC 7

		                 /* IDSEL 0x18 */
		                 c000 0 0 1 &PCI_PIC 8
		                 c000 0 0 2 &PCI_PIC 9
		                 c000 0 0 3 &PCI_PIC a
		                 c000 0 0 4 &PCI_PIC b>;

		interrupt-parent = <&PIC>;
		interrupts = <12 8>;
		ranges = <42000000 0 80000000 80000000 0 20000000
		          02000000 0 a0000000 a0000000 0 20000000
		          01000000 0 00000000 f6000000 0 02000000>;
	};

	soc@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,mpc8272", "fsl,pq2-soc";
		ranges = <00000000 f0000000 00053000>;

		// Temporary -- will go away once kernel uses ranges for get_immrbase().
		reg = <f0000000 00053000>;

		cpm@119c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
			reg = <119c0 30 0 2000>;
			ranges;

			brg@119f0 {
				compatible = "fsl,mpc8272-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <119f0 10 115f0 10>;
			};

			serial@11a00 {
				device_type = "serial";
				compatible = "fsl,mpc8272-scc-uart",
				             "fsl,cpm2-scc-uart";
				reg = <11a00 20 8000 100>;
				interrupts = <28 8>;
				interrupt-parent = <&PIC>;
				fsl,cpm-brg = <1>;
				fsl,cpm-command = <00800000>;
			};

			serial@11a60 {
				device_type = "serial";
				compatible = "fsl,mpc8272-scc-uart",
				             "fsl,cpm2-scc-uart";
				reg = <11a60 20 8300 100>;
				interrupts = <2b 8>;
				interrupt-parent = <&PIC>;
				fsl,cpm-brg = <4>;
				fsl,cpm-command = <0ce00000>;
			};

			mdio@10d40 {
				device_type = "mdio";
				compatible = "fsl,mpc8272ads-mdio-bitbang",
				             "fsl,mpc8272-mdio-bitbang",
				             "fsl,cpm2-mdio-bitbang";
				reg = <10d40 14>;
				#address-cells = <1>;
				#size-cells = <0>;
				fsl,mdio-pin = <12>;
				fsl,mdc-pin = <13>;

				PHY0: ethernet-phy@0 {
					interrupt-parent = <&PIC>;
					interrupts = <17 8>;
					reg = <0>;
					device_type = "ethernet-phy";
				};

				PHY1: ethernet-phy@1 {
					interrupt-parent = <&PIC>;
					interrupts = <17 8>;
					reg = <3>;
					device_type = "ethernet-phy";
				};
			};

			ethernet@11300 {
				device_type = "network";
				compatible = "fsl,mpc8272-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <11300 20 8400 100 11390 1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				interrupts = <20 8>;
				interrupt-parent = <&PIC>;
				phy-handle = <&PHY0>;
				linux,network-index = <0>;
				fsl,cpm-command = <12000300>;
			};

			ethernet@11320 {
				device_type = "network";
				compatible = "fsl,mpc8272-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <11320 20 8500 100 113b0 1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				interrupts = <21 8>;
				interrupt-parent = <&PIC>;
				phy-handle = <&PHY1>;
				linux,network-index = <1>;
				fsl,cpm-command = <16200300>;
			};
		};

		PIC: interrupt-controller@10c00 {
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <10c00 80>;
			compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
		};

/* May need to remove if on a part without crypto engine */
		crypto@30000 {
			device_type = "crypto";
			model = "SEC2";
			compatible = "fsl,mpc8272-talitos-sec2",
			             "fsl,talitos-sec2",
			             "fsl,talitos",
			             "talitos";
			reg = <30000 10000>;
			interrupts = <b 8>;
			interrupt-parent = <&PIC>;
			num-channels = <4>;
			channel-fifo-len = <18>;
			exec-units-mask = <0000007e>;
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
			descriptor-types-mask = <01010ebf>;
		};
	};

	chosen {
		linux,stdout-path = "/soc/cpm/serial@11a00";
	};
};

Re: device tree question

[Scott Wood]

Alan Bennett wrote:
> I want to make the mpc8272ads.dts tree work for my board.
> 
> I have an mpc8248
>   128MB Flash@ f800_0000  (Spansion S29GL512N)
>   128MB Flash@ D000_0000  (Spansion S29GL512N)
>   BCSR@e400_0000
>   2nd CSR@e410_0000
>   RAM@e420_0000
>   128MB SDRAM@[0x0..0800_0000]

What chip selects are all of these things on, and what are the 
base/length of each chip select?

> 
> Is it ok to have 0 in these:
> 	cpus {
> 		PowerPC,8272@0 {
>          . . .
> 			timebase-frequency = <0>;
> 			bus-frequency = <0>;
> 			clock-frequency = <0>;
>         . . .

Yes, the bootwrapper will fill in the proper values.

> How do I modify the following lines to match my hardware?
> 
> 	localbus@f0010100 {
>       . . .
> 		ranges = <0 0 fe000000 02000000
> 		          1 0 f4500000 00008000
> 		          3 0 f8200000 00008000>;

Put your chip select mappings here.

> 		flash@0,0 {
> 			compatible = "jedec-flash";
> 			reg = <0 0 2000000>;
> 			bank-width = <4>;
> 			device-width = <1>;
> 		};
> 
> 		board-control@1,0 {
> 			reg = <1 0 20>;
> 			compatible = "fsl,mpc8272ads-bcsr";
> 		};

Put your chip select devices here.

-Scott

Re: device tree question

[Alan Bennett]

I finally saw some light, though not much, and have made several
changes to a new dts file.

BTW: I've lost my __log_buf
  was 02aec04 now it's not there, nor is it Load Address: 0x00400000 +  02aec04


BRx/ORx=CSx
128MB flash: CS0 = F800_0000 f800_0000
128MB flash: CS4 = D000_0000 f800_0000
128MB SDRAM: CS1 = 0000_0000 f800_0000
CS2 = E400_0000 fff0_0000
CS5 = E410_0000 fff0_0000
CS6 = E420_0000 fff0_0000

/ {
	model = "MPC8248";
	compatible = "fsl,mpc8248";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8272@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <d#32>;
			i-cache-line-size = <d#32>;
			d-cache-size = <d#16384>;
			i-cache-size = <d#16384>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0 0>;
	};

	localbus@f0010100 {
		compatible = "fsl,mpc8248-localbus",
		             "fsl,pq2-localbus";
		#address-cells = <2>;
		#size-cells = <1>;
		reg = <f0010100 40>;

		ranges = <0 0 f8000000 08000000
		          1 0 f4000000 00008000
		          3 0 d0000000 08000000
			  5 0 f4100000 00100000
			  6 0 f4200000 00100000>;
		flash@0,0 {
			compatible = "jedec-flash";
			reg = <0 0 8000000>;
			bank-width = <1>;
			device-width = <32>;
		};
		board-control@1,0 {
			reg = <1 0 20>;
			compatible = "fsl,mpc8248-bcsr";
		};
		flash2@3,0 {
			compatible = "jedec-flash";
			reg = <0 0 8000000>;
			bank-width = <1>;
			device-width = <32>;
		};
		dualportram@1,0 {
			reg = <5 0 100000>;
			compatible = "fsl,mpc8248-dualportram";
		};
		dualportcsr@1,0 {
			reg = <6 0 100000>;
			compatible = "fsl,mpc8248-dualportcsr";
		};
	};

	soc@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,mpc8272", "fsl,pq2-soc";
		ranges = <00000000 f0000000 00053000>;

		// Temporary -- will go away once kernel uses ranges for get_immrbase().
		reg = <f0000000 00053000>;

		cpm@119c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
			reg = <119c0 30 0 2000>;
			ranges;

			brg@119f0 {
				compatible = "fsl,mpc8272-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <119f0 10 115f0 10>;
			};

			serial@11a00 {
				device_type = "serial";
				compatible = "fsl,mpc8272-scc-uart",
				             "fsl,cpm2-scc-uart";
				reg = <11a00 20 8000 100>;
				interrupts = <28 8>;
				interrupt-parent = <&PIC>;
				fsl,cpm-brg = <1>;
				fsl,cpm-command = <00800000>;
			};

			serial@11a82 {
				device_type = "serial";
				compatible = "fsl,mpc8272-smc-uart",
				             "fsl,cpm2-smc-uart";
				reg = <11a82 20 8300 100>;
				interrupts = <2b 8>;
				interrupt-parent = <&PIC>;
				fsl,cpm-brg = <4>;
				fsl,cpm-command = <0ce00000>;
			};

			mdio@10d40 {
				device_type = "mdio";
				compatible = "fsl,mpc8272ads-mdio-bitbang",
				             "fsl,mpc8272-mdio-bitbang",
				             "fsl,cpm2-mdio-bitbang";
				reg = <10d40 14>;
				#address-cells = <1>;
				#size-cells = <0>;
				fsl,mdio-pin = <12>;
				fsl,mdc-pin = <13>;

				PHY0: ethernet-phy@0 {
					interrupt-parent = <&PIC>;
					interrupts = <17 8>;
					reg = <0>;
					device_type = "ethernet-phy";
				};

				PHY1: ethernet-phy@1 {
					interrupt-parent = <&PIC>;
					interrupts = <17 8>;
					reg = <3>;
					device_type = "ethernet-phy";
				};
			};

			ethernet@11300 {
				device_type = "network";
				compatible = "fsl,mpc8272-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <11300 20 8400 100 11390 1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				interrupts = <20 8>;
				interrupt-parent = <&PIC>;
				phy-handle = <&PHY0>;
				linux,network-index = <0>;
				fsl,cpm-command = <12000300>;
			};

			ethernet@11320 {
				device_type = "network";
				compatible = "fsl,mpc8272-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <11320 20 8500 100 113b0 1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				interrupts = <21 8>;
				interrupt-parent = <&PIC>;
				phy-handle = <&PHY1>;
				linux,network-index = <1>;
				fsl,cpm-command = <16200300>;
			};
		};

		PIC: interrupt-controller@10c00 {
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <10c00 80>;
			compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
		};

	};

	chosen {
		linux,stdout-path = "/soc/cpm/serial@11a82";
	};
};

Re: device tree question

[Scott Wood]

Alan Bennett wrote:
> I finally saw some light, though not much, and have made several
> changes to a new dts file.
> 
> BTW: I've lost my __log_buf
>   was 02aec04 now it's not there, nor is it Load Address: 0x00400000 +  02aec04

You can't rely on that sort of thing staying at the same address... 
check System.map to see where it is now.

> BRx/ORx=CSx
> 128MB flash: CS0 = F800_0000 f800_0000
> 128MB flash: CS4 = D000_0000 f800_0000
> 128MB SDRAM: CS1 = 0000_0000 f800_0000

Below, you seem to be assuming flash is CS0 and CS3, and that CS1 is BCSR.

> / {
> 	model = "MPC8248";
> 	compatible = "fsl,mpc8248";

Model/compatible should be for the board, not the chip.

> 		board-control@1,0 {
> 			reg = <1 0 20>;
> 			compatible = "fsl,mpc8248-bcsr";
> 		};

BCSR is board-specific, not chip-specific.  The compatible should 
reference the specific board's name (with the board vendor replacing fsl).

> 		flash2@3,0 {

The unit address provides uniqueness; just do "flash@3,0".

> 			compatible = "jedec-flash";

Note that this should be cfi-flash if your flash is CFI-compatible.

> 			reg = <0 0 8000000>;
> 			bank-width = <1>;
> 			device-width = <32>;

These are specified in bytes, not bits or chips.
I'm guessing you should set them both to 4 based on the above.

> 		};
> 		dualportram@1,0 {

Should be dualportram@5,0

> 			reg = <5 0 100000>;
> 			compatible = "fsl,mpc8248-dualportram";
> 		};
> 		dualportcsr@1,0 {

Should be dualportcsr@6,0

> 	soc@f0000000 {
> 		#address-cells = <1>;
> 		#size-cells = <1>;
> 		device_type = "soc";
> 		compatible = "fsl,mpc8272", "fsl,pq2-soc";

The 8272 references should be 8248, though it doesn't currently matt

> 			serial@11a82 {
> 				device_type = "serial";
> 				compatible = "fsl,mpc8272-smc-uart",
> 				             "fsl,cpm2-smc-uart";
> 				reg = <11a82 20 8300 100>;
> 				interrupts = <2b 8>;
> 				interrupt-parent = <&PIC>;
> 				fsl,cpm-brg = <4>;
> 				fsl,cpm-command = <0ce00000>;

This doesn't look right...
You'll need to update reg, interrupts, and fsl,cpm-command for whichever 
SMC port you're using.

This is for SMC1 on the ep8248e:
	serial@11a80 {
		device_type = "serial";
		compatible = "fsl,mpc8248-smc-uart",
		             "fsl,cpm2-smc-uart";
		reg = <11a80 20 1100 40>;
		interrupts = <4 8>;
		interrupt-parent = <&PIC>;
		fsl,cpm-brg = <7>;
		fsl,cpm-command = <1d000000>;
	};

Note that the 1100 in reg should be set to wherever your firmware 
locates the SMC's parameter RAM block, and fsl,cpm-brg should be set to 
whichever BRG your firmware and/or platform code set the SMC port to.

> 			mdio@10d40 {
> 				device_type = "mdio";
> 				compatible = "fsl,mpc8272ads-mdio-bitbang",
> 				             "fsl,mpc8272-mdio-bitbang",
> 				             "fsl,cpm2-mdio-bitbang";
> 				reg = <10d40 14>;
> 				#address-cells = <1>;
> 				#size-cells = <0>;
> 				fsl,mdio-pin = <12>;
> 				fsl,mdc-pin = <13>;

Does your board do mdio the same way as the mpc8272ads board?  if not, 
you'll have to change this.

-Scott

Re: device tree question

[Alan Bennett]

[-- Attachment #1: Type: text/plain, Size: 9947 bytes --]

Ok, making progress on the ep8248 / devtrees, etc...

But I'm not getting any output on the serial and my log_buf is pretty
clean.  Without console; what's the best way to figure out why I'm not
getting any output on my SMC1 serial port (using u-boot , not planetcore)?

-Alan

__log_buf:
  Using Embedded Planet EP8248E machine description.
Linux version 2.6.23-rc6-g943401ab-dirty (root@fremont) (gcc version 3.4.5)
 #3 Wed Sep 19 12:51:18 MDT 2007.
Entering add_active_range(0, 0, 32768) 0 entries of 256 used.
Top of RAM: 0x8000000, Total RAM: 0x8000000.
Memory hole size: 0MB.
Zone PFN ranges:.
  DMA             0 ->    32768.
  Normal      32768 ->    32768.
Movable zone start PFN for each node.
early_node_map[1] active PFN ranges.
    0:        0 ->    32768.
On node 0 totalpages: 32768.
  DMA zone: 256 pages used for memmap.
  DMA zone: 0 pages reserved.
  DMA zone: 32512 pages, LIFO batch:7.
  Normal zone: 0 pages used for memmap.
  Movable zone: 0 pages used for memmap.
Built 1 zonelists in Zone order.  Total pages: 32512.
Kernel command line: root=/dev/nfs ip=192.168.10.45:::255.255.255.0::eth1
                     nfsroot=192.168.10.5:/fh/rfs rw .
PID hash table entries: 512 (order: 9, 2048 bytes).
time_init: decrementer frequency = 16.500000 MHz.
time_init: processor frequency   = 231.000000 MHz..


dts file:

/*
 * Device Tree for the Embedded Planet EP8248E board.
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/ {
        model = "EP8248E";
        compatible = "fsl,ep8248e";
        #address-cells = <1>;
        #size-cells = <1>;

        cpus {
                #address-cells = <1>;
                #size-cells = <0>;

                PowerPC,8248@0 {
                        device_type = "cpu";
                        reg = <0>;
                        d-cache-line-size = <d#32>;
                        i-cache-line-size = <d#32>;
                        d-cache-size = <d#16384>;
                        i-cache-size = <d#16384>;
                        timebase-frequency = <0>;
                        clock-frequency = <0>;
                };
        };

        CS: chipselect {
                compatible = "fsl,ep8248e-chipselect",
                             "fsl,mpc8248-chipselect",
                             "fsl,pq2-chipselect";
                #address-cells = <2>;
                #size-cells = <1>;
                fsl,ctrl = <&CSCTRL>;

                ranges = <0 0 f8000000 07f00000
                          0 1 fff00000 00080000
                          0 2 fff80000 00080000
                          1 0 e4000000 00008000
                          2 0 d0000000 08000000>;
/*  F800_0000 -> FFF0_0000  */
                flash@0,0 {
                        compatible = "cfi-flash";
                        reg = <0 0 7F00000>;
                        probe-type = "CFI";
                        bank-width = <4>;
                };
/*  FFF0_0000 -> FFF7_FFFF  */
                flash@0,1 {
                        device_type = "rom";
                        compatible = "direct-mapped";
                        reg = <0 0 80000>;
                        probe-type = "CFI";
                        bank-width = <4>;
                };
/*  FFF8_0000 -> FFFF_FFFF  */
                flash@0,2 {
                        compatible = "cfi-flash";
                        reg = <0 0 80000>;
                        probe-type = "CFI";
                        bank-width = <4>;
                };
/*  F400_0000  */
                bcsr@1,0 {
                        #address-cells = <2>;
                        #size-cells = <1>;
                        reg = <1 0 10>;
                        compatible = "fsl,ep8248e-bcsr";
                        ranges;

                        mdio {
                                device_type = "mdio";
                                compatible = "fsl,ep8248e-mdio-bitbang";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                reg = <1 8 1>;

                                PHY0: ethernet-phy@0 {
                                        interrupt-parent = <&PIC>;
                                        reg = <0>;
                                        device_type = "ethernet-phy";
                                };

                                PHY1: ethernet-phy@1 {
                                        interrupt-parent = <&PIC>;
                                        reg = <1>;
                                        device_type = "ethernet-phy";
                                };
                        };
                };
/*  D000_0000 -> D7FF_FFFF  */
                flash@2,0 {
                        compatible = "cfi-flash";
                        reg = <0 0 08000000>;
                        probe-type = "CFI";
                        bank-width = <4>;
                };
        };

        memory {
                device_type = "memory";
                reg = <0 0>;
        };

        soc@f0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
                compatible = "fsl,mpc8248", "fsl,pq2-soc";
                ranges = <00000000 f0000000 00053000>;

                CSCTRL: chipselect {
                        compatible = "fsl,mpc8248-chipselect-ctrl",
                                     "fsl,pq2-chipselect-ctrl";
                        reg = <10100 40>;
                        fsl,bus = <&CS>;
                };

                cpm@119c0 {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        #interrupt-cells = <2>;
                        compatible = "fsl,mpc8248-cpm", "fsl,cpm2";
                        reg = <119c0 30 0 1100>;
                        ranges;

                        brg@119f0 {
                                compatible = "fsl,mpc8272-brg",
                                             "fsl,cpm2-brg",
                                             "fsl,cpm-brg";
                                reg = <119f0 10 115f0 10>;
                        };

                        /* Monitor port/SMC1 */
                        serial@11a80 {
                                device_type = "serial";
                                compatible = "fsl,mpc8248-smc-uart",
                                             "fsl,cpm2-smc-uart";
                                reg = <11a80 20 1100 40>;
                                interrupts = <4 8>;
                                interrupt-parent = <&PIC>;
                                fsl,cpm-brg = <7>;
                                fsl,cpm-command = <1d000000>;
                                linux,planetcore-label = "SMC1";
                        };

                        /* "Serial" port/SCC1 */
                        serial@11a00 {
                                device_type = "serial";
                                compatible = "fsl,mpc8248-scc-uart",
                                             "fsl,cpm2-scc-uart";
                                reg = <11a00 20 8000 100>;
                                interrupts = <28 8>;
                                interrupt-parent = <&PIC>;
                                fsl,cpm-brg = <1>;
                                fsl,cpm-command = <00800000>;
                                linux,planetcore-label = "SCC1";
                        };

                        ethernet@11300 {
                                device_type = "network";
                                compatible = "fsl,mpc8248-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
                                reg = <11300 20 8400 100 11390 1>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
                                interrupts = <20 8>;
                                interrupt-parent = <&PIC>;
                                phy-handle = <&PHY0>;
                                linux,network-index = <0>;
                                fsl,cpm-command = <12000300>;
                        };

                        ethernet@11320 {
                                device_type = "network";
                                compatible = "fsl,mpc8248-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
                                reg = <11320 20 8500 100 113b0 1>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
                                interrupts = <21 8>;
                                interrupt-parent = <&PIC>;
                                phy-handle = <&PHY1>;
                                linux,network-index = <1>;
                                fsl,cpm-command = <16200300>;
                        };

                        usb@11b60 {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "fsl,mpc8248-usb",
                                             "fsl,cpm2-usb";
                                reg = <11b60 18 8b00 100>;
                                interrupt-parent = <&PIC>;
                                interrupts = <b 8>;
                                fsl,cpm-command = <2e600000>;
                        };
                };

                PIC: interrupt-controller@10c00 {
                        #interrupt-cells = <2>;
                        interrupt-controller;
                        reg = <10c00 80>;
                        compatible = "fsl,mpc8248-pic", "fsl,pq2-pic";
                };
        };
};

[-- Attachment #2: Type: text/html, Size: 33565 bytes --]

Re: device tree question

[Scott Wood]

Alan Bennett wrote:
> Ok, making progress on the ep8248 / devtrees, etc...
> 
> But I'm not getting any output on the serial and my log_buf is pretty 
> clean.  Without console; what's the best way to figure out why I'm not 
> getting any output on my SMC1 serial port (using u-boot , not planetcore)?

U-boot locates the SMC1 registers in a different place than planetcore; 
SMC1's reg property should be <11a80 20 0 40>, and the cpm's reg 
property should be <119c0 30 80 1f80>.

>         CS: chipselect {
>                 compatible = "fsl,ep8248e-chipselect",
>                              "fsl,mpc8248-chipselect",
>                              "fsl,pq2-chipselect";
>                 #address-cells = <2>;
>                 #size-cells = <1>;
>                 fsl,ctrl = <&CSCTRL>;

This has changed, and I haven't yet updated ep8248e.  The above should be:

localbus@f0010100 {
	compatible = "fsl,mpc8248-localbus",
	             "fsl,pq2-localbus";
	#address-cells = <2>;
	#size-cells = <1>;
	reg = <f0010100 40>;

You'll also need to update the bus probe matches in ep8248e.c.

>                 ranges = <0 0 f8000000 07f00000
>                           0 1 fff00000 00080000
>                           0 2 fff80000 00080000

This is wrong; the first cell is the chipselect, and the second cell is 
the offset in bytes.  I rather doubt the second flash begins at byte 1 
and the third at byte 2. :-)

>                           1 0 e4000000 00008000
>                           2 0 d0000000 08000000>;

> /*  F800_0000 -> FFF0_0000  */
>                 flash@0,0 {
>                         compatible = "cfi-flash";
>                         reg = <0 0 7F00000>;
>                         probe-type = "CFI";
>                         bank-width = <4>;
>                 };

This is a mix of the new and old flash bindings (again, I haven't yet 
updated ep8248e).  Look at the other dts files such as mpc8272ads and 
ep88xc for assistance.

> /*  F400_0000  */
>                 bcsr@1,0 {

It says e4000000 in ranges...

>                         #address-cells = <2>;
>                         #size-cells = <1>;
>                         reg = <1 0 10>;
>                         compatible = "fsl,ep8248e-bcsr";
>                         ranges;
> 
>                         mdio {
>                                 device_type = "mdio";
>                                 compatible = "fsl,ep8248e-mdio-bitbang";
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
>                                 reg = <1 8 1>;
> 
>                                 PHY0: ethernet-phy@0 {
>                                         interrupt-parent = <&PIC>;
>                                         reg = <0>;
>                                         device_type = "ethernet-phy";
>                                 };
> 
>                                 PHY1: ethernet-phy@1 {
>                                         interrupt-parent = <&PIC>;
>                                         reg = <1>;
>                                         device_type = "ethernet-phy";
>                                 };
>                         };
>                 };
> /*  D000_0000 -> D7FF_FFFF  */
>                 flash@2,0 {
>                         compatible = "cfi-flash";
>                         reg = <0 0 08000000>;

reg should be <2 0, not <0 0.

>         soc@f0000000 {
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>                 device_type = "soc";
>                 compatible = "fsl,mpc8248", "fsl,pq2-soc";
>                 ranges = <00000000 f0000000 00053000>;

You need a reg property here until the kernel uses ranges; see the 
mpc8272ads dts in my tree.

>                 CSCTRL: chipselect {
>                         compatible = "fsl,mpc8248-chipselect-ctrl",
>                                      "fsl,pq2-chipselect-ctrl";
>                         reg = <10100 40>;
>                         fsl,bus = <&CS>;
>                 };

This can go away.

-Scott

Re: device tree question

[Alan Bennett]

Device Tree and BRG?
  The SMC1 uses BRG7 and the SCC1 uses BRG1, should we have both BRGs
configured in the .dts?  ( BRG1 is configured).

Device Tree and Chosen?
  Adding a chosen block and I end up off in the weeds.  removing the
chosen block and I die within cpm_uart_console_write
        chosen {
                linux,stdout-path = "/soc/cpm/serial@11a80";
        };
  In arch/boot/ep8248e, there is a call to:
planetcore_set_stdout_path(table) is this why there is no
chosen/stdout-path element in the device tree?

  Off to back out / replace the ep8248e + planetCore code to something
more u-boot friendly.

-Alan

__log_buf when hung with ~ cpm_uart_console_write

Using Embedded Planet EP8248E machine description.
Linux version 2.6.23-rc6-g943401ab-dirty (root@fremont)
   (gcc version 3.4.5) #8 Thu Sep 20 15:03:37 MDT 2007.
Entering add_active_range(0, 0, 32768) 0 entries of 256 used.
Top of RAM: 0x8000000, Total RAM: 0x8000000.
Memory hole size: 0MB.
Zone PFN ranges:.
  DMA             0 ->    32768.
  Normal      32768 ->    32768.
Movable zone start PFN for each node.
early_node_map[1] active PFN ranges.
    0:        0 ->    32768.
On node 0 totalpages: 32768.
  DMA zone: 256 pages used for memmap.
  DMA zone: 0 pages reserved.
  DMA zone: 32512 pages, LIFO batch:7.
  Normal zone: 0 pages used for memmap.
  Movable zone: 0 pages used for memmap.
Built 1 zonelists in Zone order.  Total pages: 32512.
Kernel command line: root=/dev/nfs ip=192.168.10.45:::255.255.255.0::
  eth1 nfsroot=192.168.10.5:/fh/rfs rw .
PID hash table entries: 512 (order: 9, 2048 bytes).
time_init: decrementer frequency = 16.500000 MHz.
time_init: processor frequency   = 231.000000 MHz.
console [ttyCPM0] enabled.....


====

/*
 * Device Tree for the Embedded Planet EP8248E board.
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/ {
        model = "EP8248E";
        compatible = "fsl,ep8248e";
        #address-cells = <1>;
        #size-cells = <1>;

        cpus {
                #address-cells = <1>;
                #size-cells = <0>;

                PowerPC,8248@0 {
                        device_type = "cpu";
                        reg = <0>;
                        d-cache-line-size = <d#32>;
                        i-cache-line-size = <d#32>;
                        d-cache-size = <d#16384>;
                        i-cache-size = <d#16384>;
                        timebase-frequency = <0>;
                        clock-frequency = <0>;
                };
        };

        memory {
                device_type = "memory";
                reg = <0 0>;
        };

        localbus@f0010100 {
                compatible = "fsl,mpc8248-localbus",
                             "fsl,pq2-localbus";
                #address-cells = <2>;
                #size-cells = <1>;
                reg = <f0010100 40>;

                ranges = <0 0 f8000000 08000000
                          2 0 e4000000 00008000
                          4 0 d0000000 08000000>;

                /* CS0 F800_0000 -> FFFF_FFFF */
                flash@0,0 {  				
                        compatible = "cfi-flash";
                        reg = <0 0 08000000>;
                        bank-width = <4>;
                        device-width = <2>;
                };
                /* CS2 E400_0000 -> E400_8000 */
                board-control@2,0 {
                        compatible = "fsl,ep8248e-bcsr";
                        reg = <2 0 10>;
                        #address-cells = <2>;
                        #size-cells = <1>;
                        ranges;

                        mdio {
                                device_type = "mdio";
                                compatible = "fsl,ep8248e-mdio-bitbang";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                reg = <2 8 1>;

                                PHY0: ethernet-phy@0 {
                                        interrupt-parent = <&PIC>;
                                        reg = <0>;
                                        device_type = "ethernet-phy";
                                };

                                PHY1: ethernet-phy@1 {
                                        interrupt-parent = <&PIC>;
                                        reg = <1>;
                                        device_type = "ethernet-phy";
                                };
                        };
                };
                /* CS4 D000_0000 -> D7FF_FFFF */
                flash@4,0 {
                        compatible = "cfi-flash";
                        reg = <4 0 08000000>;
                        bank-width = <4>;
                        device-width = <2>;
                };
        };

        soc@f0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
                compatible = "fsl,mpc8248", "fsl,pq2-soc";
                ranges = <00000000 f0000000 00053000>;

                // Temporary -- will go away once kernel
                // uses ranges for get_immrbase().
                reg = <f0000000 00053000>;
                /*CPCR*/
                cpm@119c0 {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,mpc8248-cpm", "fsl,cpm2";
                        reg = <119c0 30 0 1100>;
                        ranges;

                        brg@119f0 {
                                compatible = "fsl,mpc8272-brg",
                                             "fsl,cpm2-brg",
                                             "fsl,cpm-brg";
                                reg = <119f0 10 115f0 10>;
                        };
                        /* Monitor port/SMC1 */
                        serial@11a80 {
                                device_type = "serial";
                                compatible = "fsl,mpc8248-smc-uart",
                                             "fsl,cpm2-smc-uart";
                                reg = <119c0 30 80 1f80>;      /*u-boot*/
                                interrupts = <4 8>;
                                interrupt-parent = <&PIC>;
                                fsl,cpm-brg = <7>;  /* 115F8  */
                                fsl,cpm-command = <1d000000>;
				linux,planetcore-label = "SMC1";
                        };
                        /* "Serial" port/SCC1 */
                        serial@11a00 {
                                device_type = "serial";
                                compatible = "fsl,mpc8248-scc-uart",
                                             "fsl,cpm2-scc-uart";
                                reg = <11a00 20 8000 100>;
                                interrupts = <28 8>;
                                interrupt-parent = <&PIC>;
                                fsl,cpm-brg = <1>;
                                fsl,cpm-command = <00800000>;
				linux,planetcore-label = "SCC1";
                        };

                        ethernet@11300 {
                                device_type = "network";
                                compatible = "fsl,mpc8248-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
                                reg = <11300 20 8400 100 11390 1>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
                                interrupts = <20 8>;
                                interrupt-parent = <&PIC>;
                                phy-handle = <&PHY0>;
                                linux,network-index = <0>;
                                fsl,cpm-command = <12000300>;
                        };

                        ethernet@11320 {
                                device_type = "network";
                                compatible = "fsl,mpc8248-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
                                reg = <11320 20 8500 100 113b0 1>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
                                interrupts = <21 8>;
                                interrupt-parent = <&PIC>;
                                phy-handle = <&PHY1>;
                                linux,network-index = <1>;
                                fsl,cpm-command = <16200300>;
                        };

                        usb@11b60 {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "fsl,mpc8248-usb",
                                             "fsl,cpm2-usb";
                                reg = <11b60 18 8b00 100>;
                                interrupt-parent = <&PIC>;
                                interrupts = <b 8>;
                                fsl,cpm-command = <2e600000>;
                        };
                };

                PIC: interrupt-controller@10c00 {
                        #interrupt-cells = <2>;
                        interrupt-controller;
                        reg = <10c00 80>;
                        compatible = "fsl,mpc8248-pic", "fsl,pq2-pic";
                };
        };

};

Re: device tree question

[Scott Wood]

Alan Bennett wrote:
> Device Tree and BRG?
>   The SMC1 uses BRG7 and the SCC1 uses BRG1, should we have both BRGs
> configured in the .dts?  ( BRG1 is configured).

They should both be specified, and either in the firmware or in the 
platform code you need to set CMXSMR.

> Device Tree and Chosen?
>   Adding a chosen block and I end up off in the weeds.  removing the
> chosen block and I die within cpm_uart_console_write
>         chosen {
>                 linux,stdout-path = "/soc/cpm/serial@11a80";
>         };

If you remove the chosen node, you won't get any output from the 
bootwrapper, but it shouldn't crash.

>   In arch/boot/ep8248e, there is a call to:
> planetcore_set_stdout_path(table) is this why there is no
> chosen/stdout-path element in the device tree?

The ep8248e bootwrapper platform is for planetcore (as that's what the 
board ships with).  If you're using u-boot, it's the cuboot-pq2 platform 
that you want to use.  Just make zImage and boot the cuImage.pq2 file.

-Scott