* [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range
@ 2020-03-20 10:32 Aneesh Kumar K.V
2020-03-20 15:05 ` Segher Boessenkool
2020-04-01 12:53 ` Michael Ellerman
0 siblings, 2 replies; 5+ messages in thread
From: Aneesh Kumar K.V @ 2020-03-20 10:32 UTC (permalink / raw)
To: linuxppc-dev, mpe, paulus; +Cc: Aneesh Kumar K.V
As per ISA and isync is only needed on instruction cache
block invalidate. Remove the same from dcache invalidate.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
Note: IIUC we can also void the sync fore dcbf.
arch/powerpc/include/asm/cacheflush.h | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 4a1c9f0200e1..e92191b390f3 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -65,17 +65,13 @@ static inline void flush_dcache_range(unsigned long start, unsigned long stop)
unsigned long size = stop - (unsigned long)addr + (bytes - 1);
unsigned long i;
- if (IS_ENABLED(CONFIG_PPC64)) {
+ if (IS_ENABLED(CONFIG_PPC64))
mb(); /* sync */
- isync();
- }
for (i = 0; i < size >> shift; i++, addr += bytes)
dcbf(addr);
mb(); /* sync */
- if (IS_ENABLED(CONFIG_PPC64))
- isync();
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range
2020-03-20 10:32 [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range Aneesh Kumar K.V
@ 2020-03-20 15:05 ` Segher Boessenkool
2020-03-20 15:08 ` Aneesh Kumar K.V
2020-04-01 12:53 ` Michael Ellerman
1 sibling, 1 reply; 5+ messages in thread
From: Segher Boessenkool @ 2020-03-20 15:05 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Fri, Mar 20, 2020 at 04:02:42PM +0530, Aneesh Kumar K.V wrote:
> As per ISA and isync is only needed on instruction cache
> block invalidate. Remove the same from dcache invalidate.
Is that true on older CPUs?
Segher
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range
2020-03-20 15:05 ` Segher Boessenkool
@ 2020-03-20 15:08 ` Aneesh Kumar K.V
2020-03-20 15:27 ` Segher Boessenkool
0 siblings, 1 reply; 5+ messages in thread
From: Aneesh Kumar K.V @ 2020-03-20 15:08 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
On 3/20/20 8:35 PM, Segher Boessenkool wrote:
> On Fri, Mar 20, 2020 at 04:02:42PM +0530, Aneesh Kumar K.V wrote:
>> As per ISA and isync is only needed on instruction cache
>> block invalidate. Remove the same from dcache invalidate.
>
> Is that true on older CPUs?
>
That is what I found by checking with hardware team. One thing i was not
able to get full confirmation about was the usage of 'sync' before 'dcbf'.
-aneesh
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range
2020-03-20 15:08 ` Aneesh Kumar K.V
@ 2020-03-20 15:27 ` Segher Boessenkool
0 siblings, 0 replies; 5+ messages in thread
From: Segher Boessenkool @ 2020-03-20 15:27 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Fri, Mar 20, 2020 at 08:38:42PM +0530, Aneesh Kumar K.V wrote:
> On 3/20/20 8:35 PM, Segher Boessenkool wrote:
> >On Fri, Mar 20, 2020 at 04:02:42PM +0530, Aneesh Kumar K.V wrote:
> >>As per ISA and isync is only needed on instruction cache
> >>block invalidate. Remove the same from dcache invalidate.
> >
> >Is that true on older CPUs?
> >
>
> That is what I found by checking with hardware team.
Oh, the comment right before this function says "does not invalidat
the corresponding insncache blocks", so this looks fine, sorry for not
looking closely enough before.
> One thing i was not
> able to get full confirmation about was the usage of 'sync' before 'dcbf'.
Yeah, this looks like something that would matter on some implementations.
Would it make anything measurably faster if you would remove that sync?
Segher
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range
2020-03-20 10:32 [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range Aneesh Kumar K.V
2020-03-20 15:05 ` Segher Boessenkool
@ 2020-04-01 12:53 ` Michael Ellerman
1 sibling, 0 replies; 5+ messages in thread
From: Michael Ellerman @ 2020-04-01 12:53 UTC (permalink / raw)
To: Aneesh Kumar K.V, linuxppc-dev, paulus; +Cc: Aneesh Kumar K.V
On Fri, 2020-03-20 at 10:32:42 UTC, "Aneesh Kumar K.V" wrote:
> As per ISA and isync is only needed on instruction cache
> block invalidate. Remove the same from dcache invalidate.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/233ba5461838a56c19600216f0919e7cd3aec40e
cheers
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-01 13:37 UTC | newest]
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2020-03-20 10:32 [PATCH] arch/powerpc/64: Avoid isync in flush_dcache_range Aneesh Kumar K.V
2020-03-20 15:05 ` Segher Boessenkool
2020-03-20 15:08 ` Aneesh Kumar K.V
2020-03-20 15:27 ` Segher Boessenkool
2020-04-01 12:53 ` Michael Ellerman
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