Re: NMI and AMD8131/8111 on Maple board

["tiejun.chen" <tiejun.chen@windriver.com>]

Benjamin Walsh wrote:
> Hi all,
> 
> I've written EDAC support for the AMD8131/8111 chips that are present on a
> Maple board (PPC970FX with IBM CPC925 memory controller/bridge), currently
> running in poll mode. I am now trying to get this to work in interrupt mode.
> These two chipsets have a feature that enables triggering an NMI when an
> error is detected (PERR and SERR). How can this be hooked into the interrupt
> system on a PPC board ?
> 
>>From what I understand from the doc for these chipsets, the NMI will
> delivered as a HT message to the CPC925 on this board. What I don't get is
> how will this be delivered to the CPU, and on what interrupt line ? The HT
> message sent to the CPC925 is the following:
> 
> MT = NMI
> TM = edge
> DM = physical
> INTRDEST = 'hFF (all)
> VECTOR = 'h00 (does not matter)
> 

The AMD8131/8130 can generate an NMI to the CPC925. There is an interrupt
controller resided in the CPC925. And you know the CPC925 is attached the
PowerPC PPC970FX. The interrupt controller collects and distributes system
interrupts from the PCI Express and HyperTransport blocks. So you should get the
map connection based on the system in detail. Often these information should be
defined in the corresponding dtc.

Best Regards
Tiejun

> Any help appreciated.
> 
> Thanks,
> Ben
> 
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