From: Scott Wood <scottwood@freescale.com>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev <linuxppc-dev@ozlabs.org>,
"maillist.kernel" <maillist.kernel@gmail.com>,
Trent Piepho <tpiepho@freescale.com>
Subject: Re: How to support 3GB pci address?
Date: Fri, 12 Dec 2008 11:13:45 -0600 [thread overview]
Message-ID: <49429BC9.7070508@freescale.com> (raw)
In-Reply-To: <A15C72A2-1CEE-4D22-ACA8-F0DA1F04699E@kernel.crashing.org>
Kumar Gala wrote:
>
> On Dec 12, 2008, at 3:04 AM, Trent Piepho wrote:
>
>> On Thu, 11 Dec 2008, Kumar Gala wrote:
>>> On Dec 11, 2008, at 10:07 PM, Trent Piepho wrote:
>>>> Don't the ATMU windows in the pcie controller serve as a IOMMU, making
>>>> swiotlb
>>>> unnecessary and wasteful?
>>>
>>> Nope. You have no way to tell when to switch a window as you have no
>>> idea
>>> when a device might DMA data.
>>
>> Isn't that what dma_alloc_coherent() and dma_map_single() are for?
>
> Nope. How would manipulate the PCI ATMU?
It could dynamically set up 1GB or so windows to cover
currently-established mappings as they happen, and fall back on bounce
buffering if no windows are available. This avoids penalizing a
DMA-heavy application that is the only DMA user (so no window
thrashing), but happens to live in high memory.
That said, let's get things working first, and optimize later.
-Scott
next prev parent reply other threads:[~2008-12-12 17:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-12-11 12:04 How to support 3GB pci address? maillist.kernel
2008-12-11 16:13 ` Kumar Gala
2008-12-12 4:07 ` Trent Piepho
2008-12-12 5:08 ` Kumar Gala
2008-12-12 9:04 ` Trent Piepho
2008-12-12 14:17 ` Kumar Gala
2008-12-12 17:13 ` Scott Wood [this message]
2008-12-12 20:34 ` Trent Piepho
2008-12-13 4:56 ` maillist.kernel
2008-12-13 22:11 ` Trent Piepho
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