Re: Trouble moving custom MPC8548 board to U-boot 1.3

[Pieter <phenning@vastech.co.za>]

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Hi all,
>> I have spent quite some time trying to move from U-Boot 1.2 to a newer
>> version.. I am stuck at the initialization of the ram. The ram checksum
>> fails and gives me a "total memory of 0". (the board has 512MB and work
>> when booting uboot 1.2)
>>
>> can anyone pls. point me in the right direction?
>>
>>     
> This is your root cause:  Unable to get the SPD information
> for the DDR DIMM in slot 0 of controller 0.
>
> What part are you using?  Does it support SPD?
> Is your I2C to it hooked up correctly?
> Can you dump the SPD information that is read?
> Does it match the part specs?
>
> HTH,
> jdl
I have managed to read the SPD data for the dram. I also confirmed that
the dram control and timing settings correspond to the settings that
worked in the previous uboot.
 I am now able to run uboot up to the "relocate_code". The new Stack
pointer is set to 0x0FF8DF58 witch is close enough to what i expected.
This is however where the board hangs. (The board also hang when running
the "testram").  I tried reading the data at the new stack pointer but
get "SAP: read access failed"  i get the same error when trying to read
any address within the RAM or any address of other devices.  This leads
me to think that my LAW or TLB setup is incorrect.

Looking at LAW setup: (based on board sbc8548)

    /* LAW(Local Access Window) configuration:
     * 0x0000_0000     0x1fff_ffff     DDR             512M/Auto
     * 0x8000_0000     0xbfff_ffff     PCI1 MEM        1G
     * 0xc000_0000     0xcfff_ffff     PCI1 IO         16M
     * 0xe000_0000     0xffff_ffff      LBC                       512M */
     
    struct law_entry law_table[] = {
    #ifndef CONFIG_SPD_EEPROM
            SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAWAR_SIZE_512M,
    LAWAR_TRGT_IF_DDR),
    #endif
            SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAWAR_SIZE_1G,
    LAWAR_TRGT_IF_PCI1 ),
            SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_16M,
    LAWAR_TRGT_IF_PCI1),
            SET_LAW(CONFIG_SYS_LBC_BASE, LAWAR_SIZE_512M, LAWAR_TRGT_IF_LBC)
    };

Since my board uses SPD_EEPROM, where does the LAW entry for DDR done by
cpu/mpc8xxx/ddr/util.c  and should not need changing, the base adders is
correct, as is the law_bar_target_id.

Could you pl suggest some other things i should should look at.
thanks pieter



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