mpc5200b configure nand driver via dts

mpc5200b configure nand driver via dts

[florian.belser]

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hello,
I have some problems with an mpc5200b based board. It\'s nearly
compatible to the lite5200b board.
I connected an samsung k9k8g08u0a
nand flash via the lpb bus. This works fine with an self written nand
driver. 
Now I try to use the standard nand driver from linux and
configure it via the dts file. But this doesn\'t work and I get 
the
following output:
fc000000.flash: Found 1 x16 devices at 0x0 in 16-bit
bank
 Amd/Fujitsu Extended Query Table at 0x0040
Using buffer write
method
fc000000.flash: CFI does not contain boot bank location. Assuming
top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling
erase-suspend-program due to code brokenness.
cmdlinepart partition
parsing not available
RedBoot partition parsing not available
Creating 5
MTD partitions on \"fc000000.flash\":
0x00000000-0x03d00000 :
\"fs\"
mtd: Giving out device 0 to fs
0x03d00000-0x03f00000 :
\"kernel\"
mtd: Giving out device 1 to kernel
0x03f00000-0x03f40000 :
\"u-boot\"
mtd: Giving out device 2 to u-boot
0x03f40000-0x03f60000 :
\"u-boot-env\"
mtd: Giving out device 3 to
u-boot-env
0x03f60000-0x04000000 : \"fdt\"
mtd: Giving out device 4 to
fdt
------------[ cut here ]------------
kernel BUG at
arch/powerpc/mm/pgtable_32.c:283!
Oops: Exception in kernel mode, sig: 5
[#1]
lite5200
Modules linked in:
NIP: c00132f8 LR: c00134c4 CTR:
00000000
REGS: c7827c60 TRAP: 0700   Not tainted  (2.6.28-rc6)
MSR:
00029032 <EE,ME,IR,DR>  CR: 82000022  XER: 20000000
TASK = c7828000[1]
\'swapper\' THREAD: c7826000
GPR00: f00085a9 c7827d10 c7828000 00000000
70000000 000005a9 fdff8000 c03d123c
GPR08: c7810d00 00000001 c78a0000
c9000000 00000000 ffffffff 07fbf000 07fb4e04
GPR16: 07faff18 07fb4e28
07f559f4 07f558f4 07f55844 00000001 07f557b0 07f5583b
GPR24: 00000000
c03d0000 70000000 000005a9 70000000 c9000000 c039e000 00000c90
NIP
[c00132f8] map_page+0x50/0xa8
LR [c00134c4] __ioremap+0xd0/0x158
Call
Trace:
[c7827d10] [c03d0000] 0xc03d0000 (unreliable)
[c7827d30]
[c00134c4] __ioremap+0xd0/0x158
[c7827d60] [c02ce1ec]
of_flash_probe+0xd0/0x4cc
[c7827db0] [c0209d38]
of_platform_device_probe+0x5c/0x84
[c7827dd0] [c0192df4]
driver_probe_device+0xb8/0x1e8
[c7827df0] [c0192fc8]
__driver_attach+0xa4/0xa8
[c7827e10] [c01922f8]
bus_for_each_dev+0x5c/0x98
[c7827e40] [c0192bfc]
driver_attach+0x24/0x34
[c7827e50] [c0192948]
bus_add_driver+0x1d8/0x258
[c7827e80] [c01931d8]
driver_register+0x5c/0x158
[c7827ea0] [c0209c00]
of_register_driver+0x54/0x70
[c7827eb0] [c038a5f4]
of_flash_init+0x20/0x30
[c7827ec0] [c00038e8]
do_one_initcall+0x38/0x1a4
[c7827fd0] [c0375168]
kernel_init+0x88/0xf4
[c7827ff0] [c0010a8c]
kernel_thread+0x4c/0x68
Instruction dump:
7cbb2b78 83c9f40c 7c1ff02e
7c7ff214 54090027 41820050 3d29c000 57a3b53a
7d491a15 4182005c 7c09182e
540907be <0f090000> 578b0026 540007bc 7f6b5b78
---[ end trace
4a998b56addb143e ]---
Kernel panic - not syncing: Attempted to kill
init!
Rebooting in 1 seconds..
dts lpb configuration:
lpb {
       
model =\"fsl,lpb\";
  compatible = \"fsl,lpb\",\"simple-bus\";
       
device_type = \"lpb\";
        #size-cells = <1>;
    #address-cells =
<2>;
        ranges = <0x0 0x0 0xfc000000 0x04000000
  0x1 0x0
0x70000000 0x00000100>;
  flash@0,0{  // cs0
            compatible =
\"cfi-flash\";
   #size-cells = <1>;
            #address-cells = <1>;
 
          bank-width = <2>;
            reg = <0x0 0x0 0x04000000>;
    
       partition@0 {
    label = \"fs\";
    reg = <0x00000000
0x03d00000>;
            };
            partition@3d000000 {
    label =
\"kernel\";
    reg = <0x03d00000 0x200000>;
            };
           
partition@3df00000 {
                label = \"u-boot\";
               
reg = <0x03f00000 0x40000>;
            };
            partition@3f40000
{
                label = \"u-boot-env\";
                reg=
<0x03f40000 0x20000>;
            };
            partition@3f60000 {
   
            label = \"fdt\";
                reg= <0x03f60000 0xa0000>;

           };
        };
  nand@1,0 {  //cs1
   compatible = \"samsung,
k9k8g08u08\", \"cfi-flash\";
   #size-cells = <1>;
        
#address-cells = <1>;
   bank-width = <1>;
   reg = <0x1 0x0
0x40000000>;
   partition@0 {
    label = \"nand-flash\";
    reg =
<0x00000000 0x40000000>;
   };
  };
};
Now my questions are:
 Is there
any error in the dts configuration?
 Is it principle posible to
configure a nand flash via the dts file (in combination with mpc5200b)?

I read in some forums that the nand flash must be activated in the
u-boot before it can be configured via dts. 
 This makes no sense for
me, but maybe it\'s true?
I hope you can help me with my problem and if
i made some style errors for the post, I say sorry.
Thanks a lot.
best
regards
florian belser

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Re: mpc5200b configure nand driver via dts

[Grant Likely]

On Mon, Jan 12, 2009 at 2:07 AM,  <florian.belser@freenet.de> wrote:
> hello,
>
> I have some problems with an mpc5200b based board. It's nearly compatible to
> the lite5200b board.
> I connected an samsung k9k8g08u0a nand flash via the lpb bus. This works
> fine with an self written nand driver.
> Now I try to use the standard nand driver from linux and configure it via
> the dts file. But this doesn't work and I get
> the following output:
>
>   nand@1,0 {  //cs1
>    compatible = "samsung, k9k8g08u08", "cfi-flash";
                                          ^^^^^^^^^

NAND Flash is not a CFI flash device.  The cfi-flash driver won't work with it.

> Now my questions are:
>  Is there any error in the dts configuration?
>  Is it principle posible to configure a nand flash via the dts file (in
> combination with mpc5200b)?

It is possible to *describe* the NAND flash via the dts file.  The dts
file doesn't configure anything.  It just describes the hardware
layout so that you can write or bind the appropriate driver to the
device.  I don't know if a device tree binding has been defined for
NAND flash yet.

>  I read in some forums that the nand flash must be activated in the u-boot
> before it can be configured via dts.

You definitely need to set up the CS line for the NAND before using it
in Linux.  Typically this is done in U-Boot, but in a pinch it can be
done in the platform support code (arch/powerpc/platforms/52xx/*)

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: mpc5200b configure nand driver via dts

[Wolfgang Grandegger]

Grant Likely wrote:
> On Mon, Jan 12, 2009 at 2:07 AM,  <florian.belser@freenet.de> wrote:
>> hello,
>>
>> I have some problems with an mpc5200b based board. It's nearly compatible to
>> the lite5200b board.
>> I connected an samsung k9k8g08u0a nand flash via the lpb bus. This works
>> fine with an self written nand driver.
>> Now I try to use the standard nand driver from linux and configure it via
>> the dts file. But this doesn't work and I get
>> the following output:
>>
>>   nand@1,0 {  //cs1
>>    compatible = "samsung, k9k8g08u08", "cfi-flash";
>                                           ^^^^^^^^^
> 
> NAND Flash is not a CFI flash device.  The cfi-flash driver won't work with it.
> 
>> Now my questions are:
>>  Is there any error in the dts configuration?
>>  Is it principle posible to configure a nand flash via the dts file (in
>> combination with mpc5200b)?
> 
> It is possible to *describe* the NAND flash via the dts file.  The dts
> file doesn't configure anything.  It just describes the hardware
> layout so that you can write or bind the appropriate driver to the
> device.  I don't know if a device tree binding has been defined for
> NAND flash yet.

I find 3 MTD NAND drivers with OF bindings in linux-2.6/drivers/mtd/nand

  $ grep -l of_device *.c
  fsl_elbc_nand.c
  fsl_upm.c
  pasemi_nand.c

The bindings for the FSL UPM are described in
http://lxr.linux.no/linux+v2.6.28/Documentation/powerpc/dts-bindings/fsl/upm-nand.txt.
Something similar is needed for his board (NAND connected to lpb) as well.

>>  I read in some forums that the nand flash must be activated in the u-boot
>> before it can be configured via dts.
> 
> You definitely need to set up the CS line for the NAND before using it
> in Linux.  Typically this is done in U-Boot, but in a pinch it can be
> done in the platform support code (arch/powerpc/platforms/52xx/*)

Yep, and also the R/B pin should be handled somehow, preferably using
the OF GPIO interface.

Wolfgang.

RE: Re: mpc5200b configure nand driver via dts

[florian.belser]

> > On Mon, Jan 12, 2009 at 2:07 AM,  <florian.belser@freenet.de>
> wrote:
> >> hello,
> >>
> >> I have some problems with an mpc5200b based board. It's nearly
> compatible to
> >> the lite5200b board.
> >> I connected an samsung k9k8g08u0a nand flash via the lpb bus. This
> works
> >> fine with an self written nand driver.
> >> Now I try to use the standard nand driver from linux and configure
> it via
> >> the dts file. But this doesn't work and I get
> >> the following output:
> >>
> >>   nand@1,0 {  //cs1
> >>    compatible =3D "samsung, k9k8g08u08", "cfi-flash";
> >                                           ^^^^^^^^^
> >
> > NAND Flash is not a CFI flash device.  The cfi-flash driver won't
> work with it.
Which compatible mode whould you choose ?
> >
> >> Now my questions are:
> >>  Is there any error in the dts configuration?
> >>  Is it principle posible to configure a nand flash via the dts
> file (in
> >> combination with mpc5200b)?
> >
> > It is possible to *describe* the NAND flash via the dts file.  The
> dts
> > file doesn't configure anything.  It just describes the hardware
> > layout so that you can write or bind the appropriate driver to the
> > device.  I don't know if a device tree binding has been defined for
> > NAND flash yet.
> I find 3 MTD NAND drivers with OF bindings in
> linux-2.6/drivers/mtd/nand
>=20
>   $ grep -l of_device *.c
>   fsl_elbc_nand.c
>   fsl_upm.c
>   pasemi_nand.c
>=20
> The bindings for the FSL UPM are described in
> http://lxr.linux.no/linux
v2.6.28/Documentation/powerpc/dts-bindings/fsl/upm-nand.txt.
> Something similar is needed for his board (NAND connected to lpb) as
> well.

Am I wrong or is the MTD_NAND_FSL_UPM only useable with PPC_83xx or
PPC_85xx?
>=20
> >>  I read in some forums that the nand flash must be activated in
> the u-boot
> >> before it can be configured via dts.
> >
> > You definitely need to set up the CS line for the NAND before using
> it
> > in Linux.  Typically this is done in U-Boot, but in a pinch it can
> be
> > done in the platform support code (arch/powerpc/platforms/52xx/*)
>=20
> Yep, and also the R/B pin should be handled somehow, preferably using
> the OF GPIO interface.

I set the upper named points in the u-boot, now.=20

+++ b/board/ybox/ybox.c
@@ -282,6 +282,32 @@ void flash_preinit(void)
         * executing in flash.
         */
        *(vu_long *)MPC5XXX_BOOTCS_CFG &=3D ~0x1; /* clear RO */
+
+
+       /* Configure PSC3_6 as ChipSelect for NAND Flash chip
+        set PSC3_6 pin as GPIO output */
+        *(vu_long *)MPC5XXX_GPIO_ENABLE |=3D 0x00001000; /*enable GPIO*/
+        *(vu_long *)MPC5XXX_GPIO_ODE &=3D  ~0x00001000; /* no OpenDrain
*/
+        *(vu_long *)MPC5XXX_GPIO_DIR |=3D 0x00001000; /* Direction =3D
output */
+        *(vu_long *)MPC5XXX_GPIO_DATA_O |=3D 0x00001000; /* Set CS to 1
(low active)*/
+       /* NAND config*/
+       /* Configure IRQ_0 as input for Ready/Busy pin*/
+        *(vu_long *)MPC5XXX_ICTL_EXT &=3D ~0x00000800; /*disable IRQ_0
interrupt */
+        *(vu_long *)MPC5XXX_ICTL_EXT |=3D 0x00C00000; /*low active */
+       *(vu_long *)MPC5XXX_ADDECR &=3D ~0x00020000; /*disable cs1 */
+
+        /* Configure the ChipSelect 1 on LocalPlusBus for data
transfers
+        there is a config chip select function allready, but beter do
all for nand
+        at one place */
+        /*CS1 start / end address*/
+        *(vu_long *)MPC5XXX_CS1_START =3D 0x00007000;
+        *(vu_long *)MPC5XXX_CS1_STOP =3D (0x00007000 + 0x100);
+        /*CS1 master enable */
+        *(vu_long *)MPC5XXX_CS_CTRL =3D 0x01;
+        *(vu_long *)MPC5XXX_CS1_CFG =3D 0x0f0f1800;
+       *(vu_long *)MPC5XXX_ADDECR |=3D ~0x00020000; /*enable cs1 */
+        /*enable PIN as ChipSelect*/
+        *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |=3D 0x80000000;
 }


Thanks for your replays
Best regards
Florian Belser=0A=0A=0A=0AHeute schon ge"freeMail"t?=0AJetzt kostenlose
E-Mail-Adresse
sichern!=0Ahttp://email.freenet.de/dienste/emailoffice/produktuebersicht/ba=
sic/mail/index.html?pid=3D6831=0A

Re: mpc5200b configure nand driver via dts

[Wolfgang Grandegger]

florian.belser@freenet.de wrote:
>>> On Mon, Jan 12, 2009 at 2:07 AM,  <florian.belser@freenet.de>
>> wrote:
>>>> hello,
>>>>
>>>> I have some problems with an mpc5200b based board. It's nearly
>> compatible to
>>>> the lite5200b board.
>>>> I connected an samsung k9k8g08u0a nand flash via the lpb bus. This
>> works
>>>> fine with an self written nand driver.
>>>> Now I try to use the standard nand driver from linux and configure
>> it via
>>>> the dts file. But this doesn't work and I get
>>>> the following output:
>>>>
>>>>   nand@1,0 {  //cs1
>>>>    compatible = "samsung, k9k8g08u08", "cfi-flash";
>>>                                           ^^^^^^^^^
>>>
>>> NAND Flash is not a CFI flash device.  The cfi-flash driver won't
>> work with it.
> Which compatible mode whould you choose ?

There is no mode/driver ready to use. You need to implement a MTD NAND
driver supporting the compatible "fsl,lpb-nand", similar to:

http://lxr.linux.no/linux+v2.6.28/arch/powerpc/boot/dts/mpc836x_rdk.dts#L390

>>>> Now my questions are:
>>>>  Is there any error in the dts configuration?
>>>>  Is it principle posible to configure a nand flash via the dts
>> file (in
>>>> combination with mpc5200b)?
>>> It is possible to *describe* the NAND flash via the dts file.  The
>> dts
>>> file doesn't configure anything.  It just describes the hardware
>>> layout so that you can write or bind the appropriate driver to the
>>> device.  I don't know if a device tree binding has been defined for
>>> NAND flash yet.
>> I find 3 MTD NAND drivers with OF bindings in
>> linux-2.6/drivers/mtd/nand
>>
>>   $ grep -l of_device *.c
>>   fsl_elbc_nand.c
>>   fsl_upm.c
>>   pasemi_nand.c
>>
>> The bindings for the FSL UPM are described in
>> http://lxr.linux.no/linux
> v2.6.28/Documentation/powerpc/dts-bindings/fsl/upm-nand.txt.
>> Something similar is needed for his board (NAND connected to lpb) as
>> well.
> 
> Am I wrong or is the MTD_NAND_FSL_UPM only useable with PPC_83xx or
> PPC_85xx?

That's right. The MPC5200 does *not* have an UPM.

>>>>  I read in some forums that the nand flash must be activated in
>> the u-boot
>>>> before it can be configured via dts.
>>> You definitely need to set up the CS line for the NAND before using
>> it
>>> in Linux.  Typically this is done in U-Boot, but in a pinch it can
>> be
>>> done in the platform support code (arch/powerpc/platforms/52xx/*)
>> Yep, and also the R/B pin should be handled somehow, preferably using
>> the OF GPIO interface.
> 
> I set the upper named points in the u-boot, now. 
> 
> +++ b/board/ybox/ybox.c
> @@ -282,6 +282,32 @@ void flash_preinit(void)
>          * executing in flash.
>          */
>         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
> +
> +
> +       /* Configure PSC3_6 as ChipSelect for NAND Flash chip
> +        set PSC3_6 pin as GPIO output */
> +        *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00001000; /*enable GPIO*/
> +        *(vu_long *)MPC5XXX_GPIO_ODE &=  ~0x00001000; /* no OpenDrain
> */
> +        *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00001000; /* Direction =
> output */
> +        *(vu_long *)MPC5XXX_GPIO_DATA_O |= 0x00001000; /* Set CS to 1
> (low active)*/
> +       /* NAND config*/
> +       /* Configure IRQ_0 as input for Ready/Busy pin*/
> +        *(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000800; /*disable IRQ_0
> interrupt */
> +        *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00C00000; /*low active */
> +       *(vu_long *)MPC5XXX_ADDECR &= ~0x00020000; /*disable cs1 */
> +
> +        /* Configure the ChipSelect 1 on LocalPlusBus for data
> transfers
> +        there is a config chip select function allready, but beter do
> all for nand
> +        at one place */
> +        /*CS1 start / end address*/
> +        *(vu_long *)MPC5XXX_CS1_START = 0x00007000;
> +        *(vu_long *)MPC5XXX_CS1_STOP = (0x00007000 + 0x100);
> +        /*CS1 master enable */
> +        *(vu_long *)MPC5XXX_CS_CTRL = 0x01;
> +        *(vu_long *)MPC5XXX_CS1_CFG = 0x0f0f1800;
> +       *(vu_long *)MPC5XXX_ADDECR |= ~0x00020000; /*enable cs1 */
> +        /*enable PIN as ChipSelect*/
> +        *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x80000000;
>  }

You need a dedicated MTD NAND driver for U-Boot as well.

Wolfgang.