freeze when reading a PCI bridge register

freeze when reading a PCI bridge register

[Nicolas Lavocat]

Hi everybody!

I' am trying to configure a PCI bridge on a private board, with a 
powerpc . In a first time, I tried to get informations about PCI 
devices, in order to be sure  that  my read  and write methods work ( 
using 2 configuration registers, like on an x86 architecture.) . 2 
configuration registers  are used, for example we  write  an encoded 
address (it is a request to a PCI device) in the first and the answer of 
the PCI device can be read in the second register (it is a configuration 
cycle)
Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.

For example, the code used under u-boot:

volatile u32* addr;
u32 vendor_device_ID;

puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
addr=CFG_ADDR_PCI1;
*addr=0x80007800;

addr= CFG_DATA_PCI1;
vendor_device_ID= *addr;
printf("PCI1: PCI1_VENDOR_DEVICE_ID= %08x  \n" ,vendor_device_ID);


Therefore, when I do the same thing under Linux, the system crash when I 
try to read the second register...
Linux is frozen, and there is no error message.
Under Linux, I made an ioremap before use the registers and access to 
these registers thanks to  functions  "in_be32" and "out_be32".
I tried with different endianness to avoid an error of this type.

If I understand, the main difference between u-boot and Linux (about 
registers access) is the activation of the MMU.
So I thought that  problem could come from it. 
I think the problem could came from the configuration of DBAT and IBATS 
registers of the MMU, but I didn't found any information about the MMU 
configuration under Linux.
So after this novel, I have some questions:

-Is the MMU configuration generic under Linux?
-Does somebody think that the problem doesn't come from MMU?
-How does work ioremap? Is it a fully software function, or does it 
speaks to MMU to get the effective address from physical address?
-Does somebody have an idea, or a documentation about MMU configuration 
under linux?
-Do you think that my MMU is under the control of an evil spirit? ^^

thank you for your help

Nicolas Lavocat

RE: freeze when reading a PCI bridge register

[Liu Dave-R63238]

> I' am trying to configure a PCI bridge on a private board, with a=20
> powerpc . In a first time, I tried to get informations about PCI=20
> devices, in order to be sure  that  my read  and write methods work (=20
> using 2 configuration registers, like on an x86 architecture.) . 2=20
> configuration registers  are used, for example we  write  an encoded=20
> address (it is a request to a PCI device) in the first and=20
> the answer of=20
> the PCI device can be read in the second register (it is a=20
> configuration=20
> cycle)
> Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.
>=20
> For example, the code used under u-boot:
>=20
> volatile u32* addr;
> u32 vendor_device_ID;
>=20
> puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
> addr=3DCFG_ADDR_PCI1;
> *addr=3D0x80007800;
>=20
> addr=3D CFG_DATA_PCI1;
> vendor_device_ID=3D *addr;
> printf("PCI1: PCI1_VENDOR_DEVICE_ID=3D %08x  \n" ,vendor_device_ID);
>=20
>=20
> Therefore, when I do the same thing under Linux, the system=20
> crash when I=20
> try to read the second register...
> Linux is frozen, and there is no error message.
> Under Linux, I made an ioremap before use the registers and access to=20
> these registers thanks to  functions  "in_be32" and "out_be32".
> I tried with different endianness to avoid an error of this type.
>=20
> If I understand, the main difference between u-boot and Linux (about=20
> registers access) is the activation of the MMU.
> So I thought that  problem could come from it.=20
> I think the problem could came from the configuration of DBAT=20
> and IBATS=20
> registers of the MMU, but I didn't found any information=20
> about the MMU=20
> configuration under Linux.
> So after this novel, I have some questions:
>=20
> -Is the MMU configuration generic under Linux?
> -Does somebody think that the problem doesn't come from MMU?
> -How does work ioremap? Is it a fully software function, or does it=20
> speaks to MMU to get the effective address from physical address?
> -Does somebody have an idea, or a documentation about MMU=20
> configuration=20
> under linux?
> -Do you think that my MMU is under the control of an evil spirit? ^^
>=20
What is the PowerPC you are using?

Re: freeze when reading a PCI bridge register

[Nicolas Lavocat]

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RE: freeze when reading a PCI bridge register

[Liu Dave-R63238]

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So the host bridge is important, what is the bridge?
Marvell or Tundra chipset?
 


________________________________

	From: Nicolas Lavocat [mailto:nicolas.lavocat@fr.thalesgroup.com] 
	Sent: Wednesday, April 22, 2009 4:32 PM
	To: Liu Dave-R63238
	Cc: linuxppc-dev
	Subject: Re: freeze when reading a PCI bridge register
	
	
	a 7448
	
	Liu Dave-R63238 a écrit : 

			I' am trying to configure a PCI bridge on a private board, with a 
			powerpc . In a first time, I tried to get informations about PCI 
			devices, in order to be sure  that  my read  and write methods work ( 
			using 2 configuration registers, like on an x86 architecture.) . 2 
			configuration registers  are used, for example we  write  an encoded 
			address (it is a request to a PCI device) in the first and 
			the answer of 
			the PCI device can be read in the second register (it is a 
			configuration 
			cycle)
			Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.
			
			For example, the code used under u-boot:
			
			volatile u32* addr;
			u32 vendor_device_ID;
			
			puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
			addr=CFG_ADDR_PCI1;
			*addr=0x80007800;
			
			addr= CFG_DATA_PCI1;
			vendor_device_ID= *addr;
			printf("PCI1: PCI1_VENDOR_DEVICE_ID= %08x  \n" ,vendor_device_ID);
			
			
			Therefore, when I do the same thing under Linux, the system 
			crash when I 
			try to read the second register...
			Linux is frozen, and there is no error message.
			Under Linux, I made an ioremap before use the registers and access to 
			these registers thanks to  functions  "in_be32" and "out_be32".
			I tried with different endianness to avoid an error of this type.
			
			If I understand, the main difference between u-boot and Linux (about 
			registers access) is the activation of the MMU.
			So I thought that  problem could come from it. 
			I think the problem could came from the configuration of DBAT 
			and IBATS 
			registers of the MMU, but I didn't found any information 
			about the MMU 
			configuration under Linux.
			So after this novel, I have some questions:
			
			-Is the MMU configuration generic under Linux?
			-Does somebody think that the problem doesn't come from MMU?
			-How does work ioremap? Is it a fully software function, or does it 
			speaks to MMU to get the effective address from physical address?
			-Does somebody have an idea, or a documentation about MMU 
			configuration 
			under linux?
			-Do you think that my MMU is under the control of an evil spirit? ^^
			
			    

		What is the PowerPC you are using?
		
		  


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Re: freeze when reading a PCI bridge register

[Nicolas Lavocat]

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Re: freeze when reading a PCI bridge register

[tiejun.chen]

Nicolas Lavocat wrote:
> Hi everybody!
> 
> I' am trying to configure a PCI bridge on a private board, with a
> powerpc . In a first time, I tried to get informations about PCI
> devices, in order to be sure  that  my read  and write methods work (
> using 2 configuration registers, like on an x86 architecture.) . 2
> configuration registers  are used, for example we  write  an encoded
> address (it is a request to a PCI device) in the first and the answer of
> the PCI device can be read in the second register (it is a configuration
> cycle)
> Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.
> 
> For example, the code used under u-boot:
> 
> volatile u32* addr;
> u32 vendor_device_ID;
> 
> puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
> addr=CFG_ADDR_PCI1;
> *addr=0x80007800;
> 
> addr= CFG_DATA_PCI1;
> vendor_device_ID= *addr;
> printf("PCI1: PCI1_VENDOR_DEVICE_ID= %08x  \n" ,vendor_device_ID);
> 
> 
> Therefore, when I do the same thing under Linux, the system crash when I
> try to read the second register...
> Linux is frozen, and there is no error message.
> Under Linux, I made an ioremap before use the registers and access to
> these registers thanks to  functions  "in_be32" and "out_be32".
> I tried with different endianness to avoid an error of this type.
> 
> If I understand, the main difference between u-boot and Linux (about
> registers access) is the activation of the MMU.
> So I thought that  problem could come from it. I think the problem could
> came from the configuration of DBAT and IBATS registers of the MMU, but
> I didn't found any information about the MMU configuration under Linux.
> So after this novel, I have some questions:
> 
> -Is the MMU configuration generic under Linux?
> -Does somebody think that the problem doesn't come from MMU?
> -How does work ioremap? Is it a fully software function, or does it
> speaks to MMU to get the effective address from physical address?
> -Does somebody have an idea, or a documentation about MMU configuration
> under linux?
> -Do you think that my MMU is under the control of an evil spirit? ^^
> 
> thank you for your help
> 

Looks you want to re-configure the PCI bridge again?

If so you really should do the private fixup function via some kernel API,
DECLARE_PCI_FIXUP_XXXX. It's not reasonable to re-configure PCI bridge after PCI
sub-system initial process is completed by kernel.

Best Regards
Tiejun

> Nicolas Lavocat
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
> 

Re: freeze when reading a PCI bridge register

[Nicolas Lavocat]

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Re: freeze when reading a PCI bridge register

[tiejun.chen]

Nicolas Lavocat wrote:
> In fact, because system froze, I wanted to know where was the problem, so, step 
> by step, I removed operations, until try to  read this register, basic operation 
> when a PCI device is used. This register can be read with JTAG, and under uboot, 
> so I think that it is not a PCI problem..
> 

I agreed this is not a PCI hardware problem as you said. But you want to
read/write PCI device on Linux you have to work under the Linux rules. If you
remove your PCI operation PCI works well I think MMU should be good as well.

BTW, you will make life easier for others if you can attach your crash log.

Best Regards
Tiejun

> Nicolas Lavocat
> 
> tiejun.chen a écrit :
>> Nicolas Lavocat wrote:
>>   
>>> Hi everybody!
>>>
>>> I' am trying to configure a PCI bridge on a private board, with a
>>> powerpc . In a first time, I tried to get informations about PCI
>>> devices, in order to be sure  that  my read  and write methods work (
>>> using 2 configuration registers, like on an x86 architecture.) . 2
>>> configuration registers  are used, for example we  write  an encoded
>>> address (it is a request to a PCI device) in the first and the answer of
>>> the PCI device can be read in the second register (it is a configuration
>>> cycle)
>>> Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.
>>>
>>> For example, the code used under u-boot:
>>>
>>> volatile u32* addr;
>>> u32 vendor_device_ID;
>>>
>>> puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
>>> addr=CFG_ADDR_PCI1;
>>> *addr=0x80007800;
>>>
>>> addr= CFG_DATA_PCI1;
>>> vendor_device_ID= *addr;
>>> printf("PCI1: PCI1_VENDOR_DEVICE_ID= %08x  \n" ,vendor_device_ID);
>>>
>>>
>>> Therefore, when I do the same thing under Linux, the system crash when I
>>> try to read the second register...
>>> Linux is frozen, and there is no error message.
>>> Under Linux, I made an ioremap before use the registers and access to
>>> these registers thanks to  functions  "in_be32" and "out_be32".
>>> I tried with different endianness to avoid an error of this type.
>>>
>>> If I understand, the main difference between u-boot and Linux (about
>>> registers access) is the activation of the MMU.
>>> So I thought that  problem could come from it. I think the problem could
>>> came from the configuration of DBAT and IBATS registers of the MMU, but
>>> I didn't found any information about the MMU configuration under Linux.
>>> So after this novel, I have some questions:
>>>
>>> -Is the MMU configuration generic under Linux?
>>> -Does somebody think that the problem doesn't come from MMU?
>>> -How does work ioremap? Is it a fully software function, or does it
>>> speaks to MMU to get the effective address from physical address?
>>> -Does somebody have an idea, or a documentation about MMU configuration
>>> under linux?
>>> -Do you think that my MMU is under the control of an evil spirit? ^^
>>>
>>> thank you for your help
>>>
>>>     
>>
>> Looks you want to re-configure the PCI bridge again?
>>
>> If so you really should do the private fixup function via some kernel API,
>> DECLARE_PCI_FIXUP_XXXX. It's not reasonable to re-configure PCI bridge after PCI
>> sub-system initial process is completed by kernel.
>>
>> Best Regards
>> Tiejun
>>
>>   
>>> Nicolas Lavocat
>>> _______________________________________________
>>> Linuxppc-dev mailing list
>>> Linuxppc-dev@ozlabs.org
>>> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>>>
>>>     
>>
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@ozlabs.org
>> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>>
>>   

Re: freeze when reading a PCI bridge register

[Gabriel Paubert]

On Wed, Apr 22, 2009 at 10:04:29AM +0200, Nicolas Lavocat wrote:
> Hi everybody!
>
> I' am trying to configure a PCI bridge on a private board, with a  
> powerpc . In a first time, I tried to get informations about PCI  
> devices, in order to be sure  that  my read  and write methods work (  
> using 2 configuration registers, like on an x86 architecture.) . 2  
> configuration registers  are used, for example we  write  an encoded  
> address (it is a request to a PCI device) in the first and the answer of  
> the PCI device can be read in the second register (it is a configuration  
> cycle)
> Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.

JTAG is probably a completely different hardware path, so it
does not really count. uboot testing is ok.
>
> For example, the code used under u-boot:
>
> volatile u32* addr;
> u32 vendor_device_ID;
>
> puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
> addr=CFG_ADDR_PCI1;
> *addr=0x80007800;
>
> addr= CFG_DATA_PCI1;
> vendor_device_ID= *addr;
> printf("PCI1: PCI1_VENDOR_DEVICE_ID= %08x  \n" ,vendor_device_ID);

2 possibilities:
- your I/O is not marked uncacheable (should be with ioremap)
- the PPC is reordering and issuing the read before the write,
  you should use accessors. A simple test is inserting
  an asm volatile("eieio") before the read.

About your other mails, please avoid HTML mail.

	Gabriel

Re: freeze when reading a PCI bridge register

[Nicolas Lavocat]

Thank you for your advices! I try it as soon as possible! (the board is=20
not often available...)

Nicolas Lavocat

Gabriel Paubert a =E9crit :
> On Wed, Apr 22, 2009 at 10:04:29AM +0200, Nicolas Lavocat wrote:
>  =20
>> Hi everybody!
>>
>> I' am trying to configure a PCI bridge on a private board, with a =20
>> powerpc . In a first time, I tried to get informations about PCI =20
>> devices, in order to be sure  that  my read  and write methods work ( =
=20
>> using 2 configuration registers, like on an x86 architecture.) . 2 =20
>> configuration registers  are used, for example we  write  an encoded =20
>> address (it is a request to a PCI device) in the first and the answer =
of =20
>> the PCI device can be read in the second register (it is a configurati=
on =20
>> cycle)
>> Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.
>>    =20
>
> JTAG is probably a completely different hardware path, so it
> does not really count. uboot testing is ok.
>  =20
>> For example, the code used under u-boot:
>>
>> volatile u32* addr;
>> u32 vendor_device_ID;
>>
>> puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
>> addr=3DCFG_ADDR_PCI1;
>> *addr=3D0x80007800;
>>
>> addr=3D CFG_DATA_PCI1;
>> vendor_device_ID=3D *addr;
>> printf("PCI1: PCI1_VENDOR_DEVICE_ID=3D %08x  \n" ,vendor_device_ID);
>>    =20
>
> 2 possibilities:
> - your I/O is not marked uncacheable (should be with ioremap)
> - the PPC is reordering and issuing the read before the write,
>   you should use accessors. A simple test is inserting
>   an asm volatile("eieio") before the read.
>
> About your other mails, please avoid HTML mail.
>
> 	Gabriel
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
>  =20

Re: freeze when reading a PCI bridge register

[Nicolas Lavocat]

Tests done...

-I use ioremap for the mapping of the memory, so it should be uncacheable
-I inserted a  eieio() before the read and there is no change. In=20
addition, I use outbe_32 and inbe_32, which make a sync or isync ... And=20
these functions are used for the serial port and perfectly work
about boot traces,  there is nothing to see...  system freezes just when=20
the register "pci1_cfg_addr_register" has to be read:

traces
-------------------------------------------------------------------------
[snip]
<- unflatten_device_tree()

get_real_base: looking for abac-bridge :

OF: ** translation for device /abac@20000000 **

OF: bus is default (na=3D1, ns=3D1) on /

OF: translating address: 20000000

OF: reached root node

get_real_base: base address of ABAC : 20000000

console [udbg0] enabled

setup_arch: bootmem

reading PCI vendorID and deviceID

pci1_cfg_addr =3D 0xfdfe1098, pci1_cfg_data =3D 0xfdfe1f00

writing in pci1_cfg_data_register

reading pci1_cfg_addr_register
-------------------------------------------------------------
freeze, nothing after that...

so writing seems to be ok but reading freezes...
thank you again for your suggestions ^^
If somebody has another idea...

best regards,

Nicolas Lavocat

Nicolas Lavocat a =E9crit :
> Thank you for your advices! I try it as soon as possible! (the board=20
> is not often available...)
>
> Nicolas Lavocat
>
> Gabriel Paubert a =E9crit :
>> On Wed, Apr 22, 2009 at 10:04:29AM +0200, Nicolas Lavocat wrote:
>> =20
>>> Hi everybody!
>>>
>>> I' am trying to configure a PCI bridge on a private board, with a =20
>>> powerpc . In a first time, I tried to get informations about PCI =20
>>> devices, in order to be sure  that  my read  and write methods work=20
>>> (  using 2 configuration registers, like on an x86 architecture.) .=20
>>> 2  configuration registers  are used, for example we  write  an=20
>>> encoded  address (it is a request to a PCI device) in the first and=20
>>> the answer of  the PCI device can be read in the second register (it=20
>>> is a configuration  cycle)
>>> Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.
>>>    =20
>>
>> JTAG is probably a completely different hardware path, so it
>> does not really count. uboot testing is ok.
>> =20
>>> For example, the code used under u-boot:
>>>
>>> volatile u32* addr;
>>> u32 vendor_device_ID;
>>>
>>> puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
>>> addr=3DCFG_ADDR_PCI1;
>>> *addr=3D0x80007800;
>>>
>>> addr=3D CFG_DATA_PCI1;
>>> vendor_device_ID=3D *addr;
>>> printf("PCI1: PCI1_VENDOR_DEVICE_ID=3D %08x  \n" ,vendor_device_ID);
>>>    =20
>>
>> 2 possibilities:
>> - your I/O is not marked uncacheable (should be with ioremap)
>> - the PPC is reordering and issuing the read before the write,
>>   you should use accessors. A simple test is inserting
>>   an asm volatile("eieio") before the read.
>>
>> About your other mails, please avoid HTML mail.
>>
>>     Gabriel
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@ozlabs.org
>> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>>
>>  =20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>