Re: freeze when reading a PCI bridge register

[Nicolas Lavocat <nicolas.lavocat@fr.thalesgroup.com>]

Thank you for your advices! I try it as soon as possible! (the board is=20
not often available...)

Nicolas Lavocat

Gabriel Paubert a =E9crit :
> On Wed, Apr 22, 2009 at 10:04:29AM +0200, Nicolas Lavocat wrote:
>  =20
>> Hi everybody!
>>
>> I' am trying to configure a PCI bridge on a private board, with a =20
>> powerpc . In a first time, I tried to get informations about PCI =20
>> devices, in order to be sure  that  my read  and write methods work ( =
=20
>> using 2 configuration registers, like on an x86 architecture.) . 2 =20
>> configuration registers  are used, for example we  write  an encoded =20
>> address (it is a request to a PCI device) in the first and the answer =
of =20
>> the PCI device can be read in the second register (it is a configurati=
on =20
>> cycle)
>> Firstly, I did it by JTAG: it works. Then, under uboot, it is ok.
>>    =20
>
> JTAG is probably a completely different hardware path, so it
> does not really count. uboot testing is ok.
>  =20
>> For example, the code used under u-boot:
>>
>> volatile u32* addr;
>> u32 vendor_device_ID;
>>
>> puts("PCI1 reading PCI VENDOR and DEVICE ID\n");
>> addr=3DCFG_ADDR_PCI1;
>> *addr=3D0x80007800;
>>
>> addr=3D CFG_DATA_PCI1;
>> vendor_device_ID=3D *addr;
>> printf("PCI1: PCI1_VENDOR_DEVICE_ID=3D %08x  \n" ,vendor_device_ID);
>>    =20
>
> 2 possibilities:
> - your I/O is not marked uncacheable (should be with ioremap)
> - the PPC is reordering and issuing the read before the write,
>   you should use accessors. A simple test is inserting
>   an asm volatile("eieio") before the read.
>
> About your other mails, please avoid HTML mail.
>
> 	Gabriel
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>  =20