FPGA IRQ design question

FPGA IRQ design question

[Eddie Dawydiuk]

Hello,

I'm working on a board based on the Yosemite AMCC 440EP. We have an FPGA 
connected via the PCI bus, and has an IRQ line connected directly to the 440EP. 
The FPGA implements two registers to indicate which core generated the 
interrupt. So now the question is from a design standpoint is it preferable to 
setup the IRQ as a single external IRQ then have each driver request this same 
IRQ. In each ISR the driver is responsible for checking the FPGA registers to 
see if the interrupt is intended for itself. Or would it be preferable to modify 
the lower level irq routines such that multiple software/virtual(not sure what 
the right term is here) irqs are created corresponding to the single external 
IRQ. Then abstract the details of the FPGA interrupt registers from each driver. 
Such that each driver request the proper software/virtual IRQ and requires no 
knowledge of the fpga irq registers. Any comments would be appreciated.

-- 
Best Regards,
________________________________________________________________
  Eddie Dawydiuk, Technologic Systems | voice:  (480) 837-5200
  16525 East Laser Drive 	     | fax:    (480) 837-5300
  Fountain Hills, AZ 85268            | web: www.embeddedARM.com

Re: FPGA IRQ design question

[Grant Likely]

On Wed, Apr 22, 2009 at 8:49 AM, Eddie Dawydiuk <eddie@embeddedarm.com> wrote:
> Hello,
>
> I'm working on a board based on the Yosemite AMCC 440EP. We have an FPGA
> connected via the PCI bus, and has an IRQ line connected directly to the
> 440EP. The FPGA implements two registers to indicate which core generated
> the interrupt. So now the question is from a design standpoint is it
> preferable to setup the IRQ as a single external IRQ then have each driver
> request this same IRQ. In each ISR the driver is responsible for checking
> the FPGA registers to see if the interrupt is intended for itself. Or would
> it be preferable to modify the lower level irq routines such that multiple
> software/virtual(not sure what the right term is here) irqs are created
> corresponding to the single external IRQ. Then abstract the details of the
> FPGA interrupt registers from each driver. Such that each driver request the
> proper software/virtual IRQ and requires no knowledge of the fpga irq
> registers. Any comments would be appreciated.

Both approaches are valid and you can use your judgment here, but here
are some suggestions:

If the IRQs need to be explicity acked in the FPGA iq controller, then
I'd probably write a cascaded irq driver.  Or, if you will be using
existing device drivers, then I would also probably do a cascaded
driver.

However, if you're writing one-off custom drivers and there is no
common coded needed for acking irqs, then I would probably just use
the external IRQ.

g.

Re: FPGA IRQ design question

[Eddie Dawydiuk]

Grant,

> However, if you're writing one-off custom drivers and there is no
> common coded needed for acking irqs, then I would probably just use
> the external IRQ.

Thanks for the suggestions I think going to just use the external IRQ. As a 
result I've been reading through a few different dts files to try to understand 
how/where to specify this in the dts file. I see in the Yosemite dts file the 
PCI bus device node has an interrupt-map-mask and an interrupt-map.

e.g.

PCI0: pci@ec000000 {
       device_type = "pci";
...
       /* Bamboo has all 4 IRQ pins tied together per slot */
       interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
       interrupt-map = <
            /* IDSEL 1 */
            0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
...
};

As far as I can tell this appears to be the proper location to specify that the 
PCI device(FPGA) connects an the IRQ to an external IRQ on the AMCC 440EP. I see 
where the interrupt controller(e.g. &UIC0), the interrupt number(0x1C), and the 
sense(0x8) of the external interrupt is specified. But I'm a bit puzzled by some 
of the other information.

Is this the proper place in the dts file to specify that the FPGA connects and 
external interrupt to the SoC? Can you point me to a document explaining the 
interrupt-map-mask and interrupt-map arguments?

Thanks for any pointers.

-- 
Best Regards,
________________________________________________________________
  Eddie Dawydiuk, Technologic Systems | voice:  (480) 837-5200
  16525 East Laser Drive 	     | fax:    (480) 837-5300
  Fountain Hills, AZ 85268            | web: www.embeddedARM.com

Re: FPGA IRQ design question

[Wolfgang Grandegger]

Eddie Dawydiuk wrote:
> Grant,
> 
>> However, if you're writing one-off custom drivers and there is no
>> common coded needed for acking irqs, then I would probably just use
>> the external IRQ.
> 
> Thanks for the suggestions I think going to just use the external IRQ.
> As a result I've been reading through a few different dts files to try
> to understand how/where to specify this in the dts file. I see in the
> Yosemite dts file the PCI bus device node has an interrupt-map-mask and
> an interrupt-map.
> 
> e.g.
> 
> PCI0: pci@ec000000 {
>       device_type = "pci";
> ...
>       /* Bamboo has all 4 IRQ pins tied together per slot */
>       interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
>       interrupt-map = <
>            /* IDSEL 1 */
>            0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
> ...
> };
> 
> As far as I can tell this appears to be the proper location to specify
> that the PCI device(FPGA) connects an the IRQ to an external IRQ on the
> AMCC 440EP. I see where the interrupt controller(e.g. &UIC0), the
> interrupt number(0x1C), and the sense(0x8) of the external interrupt is
> specified. But I'm a bit puzzled by some of the other information.
> 
> Is this the proper place in the dts file to specify that the FPGA
> connects and external interrupt to the SoC? Can you point me to a
> document explaining the interrupt-map-mask and interrupt-map arguments?

Yes, have a look to
http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf.

Wolfgang.