question : DMA of PCI bridge

question : DMA of PCI bridge

[Sauce.Cheng]

excuse me
I hate to bother everyone but I have a question about DMA of PCI bridge

Now I attempt to fetch data from peripheral device to SDRAM, and it has been
successed

but how the DMA controller know the data bandwidth of src and dest.

for example, if i get a 16bits data with a 32bits bus, and other 16bits will
be set high
and data will fetched into cache line of dma, then it will be wrote to
32bits SDRAM.

i guess the data will be wrong, isn't ?

please give me some advices. thank you

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Re: question : DMA of PCI bridge

[David Hawkins]

Hi,

> Now I attempt to fetch data from peripheral device to SDRAM, and it has been
> successed
> 
> but how the DMA controller know the data bandwidth of src and dest.
> 
> for example, if i get a 16bits data with a 32bits bus, and other 16bits will
> be set high
> and data will fetched into cache line of dma, then it will be wrote to
> 32bits SDRAM.

You'll need to give us a little more detail. For example,
what processor are you using to perform the transaction?

Your email title says DMA of PCI bridge, however, you
mention peripheral to SDRAM. Are you using a DMA controller
on the peripheral, eg. a PCI bus master, to DMA into the
host SDRAM, or are you using a host DMA controller to
DMA over PCI into memory on the host?

Whether or not you get packing bytes when you access a
16-bit device and transfer the data to a 32-bit destination
depends on how the device is mapped. For example, a 16-bit
device can be implemented such that it responds to 8-bit,
16-bit, and 32-bit requests, but the 32-bit requests will
require more wait-states, since the device has to be
read from twice before constructing a 32-bit word to
place on the PCI bus.

Its also possible that the DMA controller can be configured
to deal with different source and destination widths. However
without knowing what processor or DMA controller you are
asking about, theres not much to say.

Cheers,
Dave

Re: question : DMA of PCI bridge

[Sauce.Cheng]

thank you dave for your reply 

my processor is MPC8247, on Linux 2.6.11


in MPC8247 manual reference, the interrupt of DMA unit belonged PCI bridge.
that is different from SDMA and IDMA. through i do not know what 's the
different. heard SDMA is used to transfer between CPM and 60x. DMA is used
to transfer between 60x bus and PCI, or 60x bus - 60x bus. i am not sure.

> Whether or not you get packing bytes when you access a
> 16-bit device and transfer the data to a 32-bit destination
> depends on how the device is mapped. For example, a 16-bit
> device can be implemented such that it responds to 8-bit,
> 16-bit, and 32-bit requests, but the 32-bit requests will
> require more wait-states, since the device has to be
> read from twice before constructing a 32-bit word to
> place on the PCI bus.

ya, that's it

> Its also possible that the DMA controller can be configured
> to deal with different source and destination widths. However
> without knowing what processor or DMA controller you are
> asking about, theres not much to say.

in the manual reference charpter 9.13 DMA,  source and destination address
can be configured. i can not find the hint about source and destination
widths configured.
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Re: question : DMA of PCI bridge

[David Hawkins]

Hi,

> my processor is MPC8247, on Linux 2.6.11
> 
> in MPC8247 manual reference, the interrupt of DMA unit belonged PCI bridge.
> that is different from SDMA and IDMA. through i do not know what 's the
> different. heard SDMA is used to transfer between CPM and 60x. DMA is used
> to transfer between 60x bus and PCI, or 60x bus - 60x bus. i am not sure.
> 
>> Whether or not you get packing bytes when you access a
>> 16-bit device and transfer the data to a 32-bit destination
>> depends on how the device is mapped. For example, a 16-bit
>> device can be implemented such that it responds to 8-bit,
>> 16-bit, and 32-bit requests, but the 32-bit requests will
>> require more wait-states, since the device has to be
>> read from twice before constructing a 32-bit word to
>> place on the PCI bus.
> 
> ya, that's it
> 
>> Its also possible that the DMA controller can be configured
>> to deal with different source and destination widths. However
>> without knowing what processor or DMA controller you are
>> asking about, theres not much to say.
> 
> in the manual reference charpter 9.13 DMA,  source and destination address
> can be configured. i can not find the hint about source and destination
> widths configured.


I won't have a chance to look at the MPC8247 manual, so
I'll just give a general comment.

If you are DMAing from an internal peripheral, then it's
width will be hard-coded and can be read from the user-manual.

If you are DMAing from a local bus then the local bus definition
should determine what happens. For example, on the MPC8349, you
can put 16-bit flash on the local bus, and configure the local
bus controller to know that it is 16-bits wide. A 32-bit access
by the CPU or DMA controller will generate two reads on the
local bus.

You can investigate to see whether the MPC8247 works similarly.

Cheers,
Dave

Re: question : DMA of PCI bridge

[Sauce.Cheng]

>
> in the manual reference charpter 9.13 DMA, source and destination address

> If you are DMAing from an internal peripheral, then it's
> width will be hard-coded and can be read from the user-manual.

you mean it will be set by hard circuit ? maybe i should talk with your hard
engineer.
but as you say, the width will be hard-coded, mean that the width can not be
changed ? 
it can fetch 16 bits to 32bits, can not tetch 16bits to 16bits ?

i am sorry about my poor English, i am not sure if i expressed clearly


> If you are DMAing from a local bus then the local bus definition
> should determine what happens. For example, on the MPC8349, you
> can put 16-bit flash on the local bus, and configure the local
> bus controller to know that it is 16-bits wide. A 32-bit access
> by the CPU or DMA controller will generate two reads on the
> local bus.

that's right, BRx and ORx should be configured for setting width, but that
is bus width, not data width. or bus width should be equal to data width
what fetch from the bus ?

> You can investigate to see whether the MPC8247 works similarly.
all right, i will , thanks a lot

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