From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 89E63B7BA3 for ; Fri, 28 Aug 2009 01:58:50 +1000 (EST) Received: from az33egw02.freescale.net (az33egw02.freescale.net [192.88.158.103]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "az33egw02.freescale.net", Issuer "Thawte Premium Server CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id C4116DDD0B for ; Fri, 28 Aug 2009 01:58:48 +1000 (EST) Message-ID: <4A96AD4B.1010204@freescale.com> Date: Thu, 27 Aug 2009 10:59:07 -0500 From: Scott Wood MIME-Version: 1.0 To: "wilbur.chan" Subject: Re: Can't write value into memory ?(E500 V2) References: <20090826192030.GA17027@b07421-ec1.am.freescale.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Cc: linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , wilbur.chan wrote: > I am using a SMP E500 v2, and I want CPU0 to write some value to a > physical address, and wait for CPU1 to read from it. Is this under Linux (it is a Linux mailing list...)? If so, there are better ways of communicating that don't involve clobbering random memory and overlapping userspace TLB mappings. > However, it seemed failed to communicate between CPUs by DRAM.. CPU1 > can not read > > the correct value from the address where CPU1 wrote to. Do both cores have a mapping with the M bit (memory coherence required) set? -Scott