From: Wolfgang Grandegger <wg@grandegger.com>
To: Felix Radensky <felix@embedded-sol.com>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: I2C bus clock on MPC85XX systems
Date: Tue, 22 Dec 2009 17:18:45 +0100 [thread overview]
Message-ID: <4B30F165.2060300@grandegger.com> (raw)
In-Reply-To: <4B30E7F5.8080201@embedded-sol.com>
Felix Radensky wrote:
> Hi,
>
> Almost all MPC85XX based systems have the compatible=:"fsl-i2c" in
> respective
> i2c device tree nodes. This causes FSL i2c driver to use the following
> "backward
> compatible" values: FSR=0x31 DFSR=0x10. This is regardless of CCB clock
> frequency and i2c clock prescaler.
>
> On my custom MPC8536 based board with 432MHz CCB clock this results in
> 65KHz i2c clock frequency (checked with scope). U-Boot correctly configures
> the clock to 400KHz.
>
> I've fixed the problem by modifying device tree to use different
> compatible value,
> similar to what socrates board does. Is this the right approach ?
Are you aware of the properties described in
"Documentation/powerpc/dts-bindings/fsl/i2c.txt":
http://lxr.linux.no/#linux+v2.6.32/Documentation/powerpc/dts-bindings/fsl/i2c.txt
Wolfgang.
next prev parent reply other threads:[~2009-12-22 16:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-12-22 15:38 I2C bus clock on MPC85XX systems Felix Radensky
2009-12-22 16:18 ` Wolfgang Grandegger [this message]
2009-12-22 18:16 ` Felix Radensky
2009-12-22 18:40 ` Wolfgang Grandegger
2009-12-22 19:06 ` Felix Radensky
2009-12-22 19:20 ` Wolfgang Grandegger
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