From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from VA3EHSOBE009.bigfish.com (mail-va3.bigfish.com [216.32.180.10]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id D32561007D4 for ; Sat, 12 Nov 2011 03:39:31 +1100 (EST) From: Tabi Timur-B04825 To: "Kokoris, Ioannis" Subject: Re: [PATCH] P1021: set IReady in QE Microcode Upload Date: Fri, 11 Nov 2011 16:39:21 +0000 Message-ID: <4EBD4FB8.2020406@freescale.com> References: <026483A88B848047A08C3F03E20822D0267B1F4A55@MCHP058A.global-ad.net> In-Reply-To: <026483A88B848047A08C3F03E20822D0267B1F4A55@MCHP058A.global-ad.net> Content-Type: text/plain; charset="iso-8859-1" MIME-Version: 1.0 Cc: "linuxppc-dev@lists.ozlabs.org" , Tabi Timur-B04825 , "linux-kernel@vger.kernel.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Kokoris, Ioannis wrote: > Hi, > > QE Microcode Initialization using qe_upload_microcode() does not work > on P1021 if the IRAM-Ready register is not set after the microcode > upload. This patch adds a definition for the "I-RAM Ready" register and > sets it uppon microcode upload completion. Will this code still work on other QE parts, like the MPC8323? --=20 Timur Tabi Linux kernel developer at Freescale=