[PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Roy Zang]

P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
shared with PCIe controller.
The silicon internally ties the interrupts to L, so change the
IRQ[4:6,11] to high level sensitive for PCIe.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
 arch/powerpc/boot/dts/p1023rds.dts |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
index d9b7767..66bf804 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -490,9 +490,9 @@
 			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map = <
 				/* IDSEL 0x0 */
-				0000 0 0 1 &mpic 4 1
-				0000 0 0 2 &mpic 5 1
-				0000 0 0 3 &mpic 6 1
+				0000 0 0 1 &mpic 4 2
+				0000 0 0 2 &mpic 5 2
+				0000 0 0 3 &mpic 6 2
 				0000 0 0 4 &mpic 7 1
 				>;
 			ranges = <0x2000000 0x0 0xa0000000
@@ -532,7 +532,7 @@
 				0000 0 0 1 &mpic 8 1
 				0000 0 0 2 &mpic 9 1
 				0000 0 0 3 &mpic 10 1
-				0000 0 0 4 &mpic 11 1
+				0000 0 0 4 &mpic 11 2
 				>;
 			ranges = <0x2000000 0x0 0x80000000
 				  0x2000000 0x0 0x80000000
-- 
1.6.0.6

Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Scott Wood]

On 11/07/2011 02:32 AM, Roy Zang wrote:
> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.

Some extra commentary on why this works would be nice.

The manual says:

> If a PCI Express INTx interrupt is being used, then the PIC must be configured so that external interrupts
> are level-sensitive (EIVPRn[S] = 1).

and

> In general, these signals should be considered mutually exclusive. If a PCI Express INTx signal is being
> used, the PIC must be configured so that external interrupts are level sensitive (EIVPRn[S] = 1). If an IRQn
> signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not allow inbound PCI Express
> INTx transactions.
>
> Note that it is possible to share IRQn and INTx if the external interrupt is level sensitive; however, if an
> interrupt occurs, the interrupt service routine must poll both the external sources connected to the IRQn
> input and the PCI Express INTx sources to determine from which path the external interrupt came. In any
> case, IRQn should be pulled to the negated state as determined by the associated polarity setting in
> EIVPRn[P].

So it looks like there's some magic whereby the configuration of the
MPIC affects how the PCIe feeds the interrupt in.

Is there (or will there be) an erratum, or anything in the manual
besides not being documented as external interrupts, about these
specific interrupts being tied low in silicon or needing to be active high?

-Scott

RE: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogVHVlc2RheSwgTm92ZW1iZXIgMDgsIDIwMTEgMjo0NCBBTQ0KPiBUbzogWmFu
ZyBSb3ktUjYxOTExDQo+IENjOiBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZw0KPiBTdWJq
ZWN0OiBSZTogW1BBVENIXSBwb3dlcnBjL3AxMDIzOiBzZXQgSVJRWzQ6NiwgMTFdIHRvIGhpZ2gg
bGV2ZWwgc2Vuc2l0aXZlIGZvcg0KPiBQQ0llDQo+IA0KPiBPbiAxMS8wNy8yMDExIDAyOjMyIEFN
LCBSb3kgWmFuZyB3cm90ZToNCj4gPiBQMTAyMyBleHRlcm5hbCBJUlFbNDo2LCAxMV0gZG8gbm90
IHBpbiBvdXQsIGJ1dCB0aGUgaW50ZXJydXB0cyBhcmUNCj4gPiBzaGFyZWQgd2l0aCBQQ0llIGNv
bnRyb2xsZXIuDQo+ID4gVGhlIHNpbGljb24gaW50ZXJuYWxseSB0aWVzIHRoZSBpbnRlcnJ1cHRz
IHRvIEwsIHNvIGNoYW5nZSB0aGUNCj4gPiBJUlFbNDo2LDExXSB0byBoaWdoIGxldmVsIHNlbnNp
dGl2ZSBmb3IgUENJZS4NCj4gDQo+IFNvbWUgZXh0cmEgY29tbWVudGFyeSBvbiB3aHkgdGhpcyB3
b3JrcyB3b3VsZCBiZSBuaWNlLg0KSSBkbyBub3Qga25vdyB3aGF0IGtpbmQgb2YgZXh0cmEgY29t
bWVudGFyeSB5b3UgcmVxdWVzdC4gDQpJUlEgNCw1LDYsIDExIGFyZSBpbnRlcm5hbGx5IHRpZSB0
byBsb3cgYnkgc2lsaWNvbi4gVG8gdXNlIHRoZXNlIGludGVycnVwdHMgZm9yIFBDSWUsIHRoZXkg
bmVlZCB0byBzZXQgaGlnaCBsZXZlbCBzZW5zaXRpdmUuDQpJdCBpcyBjbGVhciBlbm91Z2ggZm9y
IHRoaXMgcGF0Y2guDQoNCj4gDQo+IFRoZSBtYW51YWwgc2F5czoNCj4gDQo+ID4gSWYgYSBQQ0kg
RXhwcmVzcyBJTlR4IGludGVycnVwdCBpcyBiZWluZyB1c2VkLCB0aGVuIHRoZSBQSUMgbXVzdCBi
ZSBjb25maWd1cmVkDQo+IHNvIHRoYXQgZXh0ZXJuYWwgaW50ZXJydXB0cw0KPiA+IGFyZSBsZXZl
bC1zZW5zaXRpdmUgKEVJVlBSbltTXSA9IDEpLg0KVGhhdCBpcyB0cnVlIGZvciBhbGwgRlNMIHBv
d2VycGMgc2lsaWNvbiB3aXRoIFBDSWUgY29udHJvbGxlciBiZXNpZGUgUDEwMjMuDQoNCj4gDQo+
IGFuZA0KPiANCj4gPiBJbiBnZW5lcmFsLCB0aGVzZSBzaWduYWxzIHNob3VsZCBiZSBjb25zaWRl
cmVkIG11dHVhbGx5IGV4Y2x1c2l2ZS4gSWYgYSBQQ0kNCj4gRXhwcmVzcyBJTlR4IHNpZ25hbCBp
cyBiZWluZw0KPiA+IHVzZWQsIHRoZSBQSUMgbXVzdCBiZSBjb25maWd1cmVkIHNvIHRoYXQgZXh0
ZXJuYWwgaW50ZXJydXB0cyBhcmUgbGV2ZWwNCj4gc2Vuc2l0aXZlIChFSVZQUm5bU10gPSAxKS4g
SWYgYW4gSVJRbg0KPiA+IHNpZ25hbCBpcyBiZWluZyB1c2VkIGFzIGVkZ2UtdHJpZ2dlcmVkIChF
SVZQUm5bU10gPSAwKSwgdGhlIHN5c3RlbSBtdXN0IG5vdA0KPiBhbGxvdyBpbmJvdW5kIFBDSSBF
eHByZXNzDQo+ID4gSU5UeCB0cmFuc2FjdGlvbnMuDQo+ID4NCj4gPiBOb3RlIHRoYXQgaXQgaXMg
cG9zc2libGUgdG8gc2hhcmUgSVJRbiBhbmQgSU5UeCBpZiB0aGUgZXh0ZXJuYWwgaW50ZXJydXB0
IGlzDQo+IGxldmVsIHNlbnNpdGl2ZTsgaG93ZXZlciwgaWYgYW4NCj4gPiBpbnRlcnJ1cHQgb2Nj
dXJzLCB0aGUgaW50ZXJydXB0IHNlcnZpY2Ugcm91dGluZSBtdXN0IHBvbGwgYm90aCB0aGUgZXh0
ZXJuYWwNCj4gc291cmNlcyBjb25uZWN0ZWQgdG8gdGhlIElSUW4NCj4gPiBpbnB1dCBhbmQgdGhl
IFBDSSBFeHByZXNzIElOVHggc291cmNlcyB0byBkZXRlcm1pbmUgZnJvbSB3aGljaCBwYXRoIHRo
ZQ0KPiBleHRlcm5hbCBpbnRlcnJ1cHQgY2FtZS4gSW4gYW55DQo+ID4gY2FzZSwgSVJRbiBzaG91
bGQgYmUgcHVsbGVkIHRvIHRoZSBuZWdhdGVkIHN0YXRlIGFzIGRldGVybWluZWQgYnkgdGhlDQo+
IGFzc29jaWF0ZWQgcG9sYXJpdHkgc2V0dGluZyBpbg0KPiA+IEVJVlBSbltQXS4NCj4gDQo+IFNv
IGl0IGxvb2tzIGxpa2UgdGhlcmUncyBzb21lIG1hZ2ljIHdoZXJlYnkgdGhlIGNvbmZpZ3VyYXRp
b24gb2YgdGhlDQo+IE1QSUMgYWZmZWN0cyBob3cgdGhlIFBDSWUgZmVlZHMgdGhlIGludGVycnVw
dCBpbi4NCj4gDQo+IElzIHRoZXJlIChvciB3aWxsIHRoZXJlIGJlKSBhbiBlcnJhdHVtLCBvciBh
bnl0aGluZyBpbiB0aGUgbWFudWFsDQo+IGJlc2lkZXMgbm90IGJlaW5nIGRvY3VtZW50ZWQgYXMg
ZXh0ZXJuYWwgaW50ZXJydXB0cywgYWJvdXQgdGhlc2UNCj4gc3BlY2lmaWMgaW50ZXJydXB0cyBi
ZWluZyB0aWVkIGxvdyBpbiBzaWxpY29uIG9yIG5lZWRpbmcgdG8gYmUgYWN0aXZlIGhpZ2g/DQpJ
IGRvIG5vdCB0aGluayB0aGVyZSBpcyAod2lsbCkgYW4gZXJyYXR1bS4gQnV0IEkgYWdyZWUgdGhl
IG1hbnVhbCBuZWVkcyB0byBkb2N1bWVudCB0aGlzIG1vcmUgY2xlYXIuDQp0aGFua3MuDQpSb3kN
Cg0K

Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Scott Wood]

On 11/07/2011 11:51 PM, Zang Roy-R61911 wrote:
> 
> 
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Tuesday, November 08, 2011 2:44 AM
>> To: Zang Roy-R61911
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
>> PCIe
>>
>> On 11/07/2011 02:32 AM, Roy Zang wrote:
>>> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
>>> shared with PCIe controller.
>>> The silicon internally ties the interrupts to L, so change the
>>> IRQ[4:6,11] to high level sensitive for PCIe.
>>
>> Some extra commentary on why this works would be nice.
> I do not know what kind of extra commentary you request. 

Just a note that there's magic to allow the PCIe block to output these
interrupts as either active-high or active-low, depending on how they're
configured at the mpic.

> IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts for PCIe, they need to set high level sensitive.
> It is clear enough for this patch.

It's odd enough that I felt the need to go reading through the docs to
see why such a thing would work at all.

>> The manual says:
>>
>>> If a PCI Express INTx interrupt is being used, then the PIC must be configured
>> so that external interrupts
>>> are level-sensitive (EIVPRn[S] = 1).
> That is true for all FSL powerpc silicon with PCIe controller beside P1023.

Sure, my point was more that it didn't say anything there about how to
configure EIVPRn[P].

-Scott

RE: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Zang Roy-R61911]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogV2VkbmVzZGF5LCBOb3ZlbWJlciAwOSwgMjAxMSAwOjU0IEFNDQo+IFRvOiBa
YW5nIFJveS1SNjE5MTENCj4gQ2M6IFdvb2QgU2NvdHQtQjA3NDIxOyBsaW51eHBwYy1kZXZAbGlz
dHMub3psYWJzLm9yZw0KPiBTdWJqZWN0OiBSZTogW1BBVENIXSBwb3dlcnBjL3AxMDIzOiBzZXQg
SVJRWzQ6NiwgMTFdIHRvIGhpZ2ggbGV2ZWwgc2Vuc2l0aXZlIGZvcg0KPiBQQ0llDQo+IA0KPiBP
biAxMS8wNy8yMDExIDExOjUxIFBNLCBaYW5nIFJveS1SNjE5MTEgd3JvdGU6DQo+ID4NCj4gPg0K
PiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+PiBGcm9tOiBXb29kIFNjb3R0LUIw
NzQyMQ0KPiA+PiBTZW50OiBUdWVzZGF5LCBOb3ZlbWJlciAwOCwgMjAxMSAyOjQ0IEFNDQo+ID4+
IFRvOiBaYW5nIFJveS1SNjE5MTENCj4gPj4gQ2M6IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMu
b3JnDQo+ID4+IFN1YmplY3Q6IFJlOiBbUEFUQ0hdIHBvd2VycGMvcDEwMjM6IHNldCBJUlFbNDo2
LCAxMV0gdG8gaGlnaCBsZXZlbCBzZW5zaXRpdmUNCj4gZm9yDQo+ID4+IFBDSWUNCj4gPj4NCj4g
Pj4gT24gMTEvMDcvMjAxMSAwMjozMiBBTSwgUm95IFphbmcgd3JvdGU6DQo+ID4+PiBQMTAyMyBl
eHRlcm5hbCBJUlFbNDo2LCAxMV0gZG8gbm90IHBpbiBvdXQsIGJ1dCB0aGUgaW50ZXJydXB0cyBh
cmUNCj4gPj4+IHNoYXJlZCB3aXRoIFBDSWUgY29udHJvbGxlci4NCj4gPj4+IFRoZSBzaWxpY29u
IGludGVybmFsbHkgdGllcyB0aGUgaW50ZXJydXB0cyB0byBMLCBzbyBjaGFuZ2UgdGhlDQo+ID4+
PiBJUlFbNDo2LDExXSB0byBoaWdoIGxldmVsIHNlbnNpdGl2ZSBmb3IgUENJZS4NCj4gPj4NCj4g
Pj4gU29tZSBleHRyYSBjb21tZW50YXJ5IG9uIHdoeSB0aGlzIHdvcmtzIHdvdWxkIGJlIG5pY2Uu
DQo+ID4gSSBkbyBub3Qga25vdyB3aGF0IGtpbmQgb2YgZXh0cmEgY29tbWVudGFyeSB5b3UgcmVx
dWVzdC4NCj4gDQo+IEp1c3QgYSBub3RlIHRoYXQgdGhlcmUncyBtYWdpYyB0byBhbGxvdyB0aGUg
UENJZSBibG9jayB0byBvdXRwdXQgdGhlc2UNCj4gaW50ZXJydXB0cyBhcyBlaXRoZXIgYWN0aXZl
LWhpZ2ggb3IgYWN0aXZlLWxvdywgZGVwZW5kaW5nIG9uIGhvdyB0aGV5J3JlDQo+IGNvbmZpZ3Vy
ZWQgYXQgdGhlIG1waWMuDQpJIGRvIG5vdCB0aGluayB0aGVyZSBpcyBhbnkgbWFnaWMuDQpPbiB0
aGUgY29udHJhcnksIGl0IGlzIHRoZSBtcGljL2RldmljZSB0cmVlIG5lZWRzIHRvIGNvbXBseSB3
aXRoIHRoZSBoYXJkd2FyZSBzZXR0aW5nIGZvciB0aGUgaW50ZXJydXB0IHBvbGFyaXR5Lg0KDQo+
IA0KPiA+IElSUSA0LDUsNiwgMTEgYXJlIGludGVybmFsbHkgdGllIHRvIGxvdyBieSBzaWxpY29u
LiBUbyB1c2UgdGhlc2UgaW50ZXJydXB0cw0KPiBmb3IgUENJZSwgdGhleSBuZWVkIHRvIHNldCBo
aWdoIGxldmVsIHNlbnNpdGl2ZS4NCj4gPiBJdCBpcyBjbGVhciBlbm91Z2ggZm9yIHRoaXMgcGF0
Y2guDQo+IA0KPiBJdCdzIG9kZCBlbm91Z2ggdGhhdCBJIGZlbHQgdGhlIG5lZWQgdG8gZ28gcmVh
ZGluZyB0aHJvdWdoIHRoZSBkb2NzIHRvDQo+IHNlZSB3aHkgc3VjaCBhIHRoaW5nIHdvdWxkIHdv
cmsgYXQgYWxsLg0KSWYgeW91IGNvbnNpZGVyIHRoZSBub3JtYWwgY2FzZSwgdGhlIHNoYXJlZCBp
cnEgcHVsbHMgdXAsIHRoZSBQQ0llIGludGVycnVwdCBzZXQgdG8gbG93IGxldmVsIHNlbnNpdGl2
ZS4gQW55dGhpbmcgb2RkPw0KDQo+IA0KPiA+PiBUaGUgbWFudWFsIHNheXM6DQo+ID4+DQo+ID4+
PiBJZiBhIFBDSSBFeHByZXNzIElOVHggaW50ZXJydXB0IGlzIGJlaW5nIHVzZWQsIHRoZW4gdGhl
IFBJQyBtdXN0IGJlDQo+IGNvbmZpZ3VyZWQNCj4gPj4gc28gdGhhdCBleHRlcm5hbCBpbnRlcnJ1
cHRzDQo+ID4+PiBhcmUgbGV2ZWwtc2Vuc2l0aXZlIChFSVZQUm5bU10gPSAxKS4NCj4gPiBUaGF0
IGlzIHRydWUgZm9yIGFsbCBGU0wgcG93ZXJwYyBzaWxpY29uIHdpdGggUENJZSBjb250cm9sbGVy
IGJlc2lkZSBQMTAyMy4NCj4gDQo+IFN1cmUsIG15IHBvaW50IHdhcyBtb3JlIHRoYXQgaXQgZGlk
bid0IHNheSBhbnl0aGluZyB0aGVyZSBhYm91dCBob3cgdG8NCj4gY29uZmlndXJlIEVJVlBSbltQ
XS4NCkl0IGRlcGVuZHMgb24gdGhlIGlycSBwdWxscyB1cCBvciBkb3duIGJ5IGhhcmR3YXJlLg0K
Um95DQo=

Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Scott Wood]

On Wed, Nov 09, 2011 at 09:27:02AM -0600, Zang Roy-R61911 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Wednesday, November 09, 2011 0:54 AM
> > To: Zang Roy-R61911
> > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
> > PCIe
> > 
> > Just a note that there's magic to allow the PCIe block to output these
> > interrupts as either active-high or active-low, depending on how they're
> > configured at the mpic.
> I do not think there is any magic.
> On the contrary, it is the mpic/device tree needs to comply with the hardware setting for the interrupt polarity.

The magic is that the PCIe block can generate the interrupt in either
polarity depending on the MPIC setting (or perhaps it bases it on
sampling the pin status during/after reset, but that seems fragile).

> > > IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts
> > for PCIe, they need to set high level sensitive.
> > > It is clear enough for this patch.
> > 
> > It's odd enough that I felt the need to go reading through the docs to
> > see why such a thing would work at all.
> If you consider the normal case, the shared irq pulls up, the PCIe interrupt set to low level sensitive. Anything odd?

The oddity is that active-high works at all for a PCI interrupt, and that
not all the PCIe interrupts have the same polarity.

-Scott

Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Kumar Gala]

How did you come by this information?

- k

On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:

> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.
>=20
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> arch/powerpc/boot/dts/p1023rds.dts |    8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/powerpc/boot/dts/p1023rds.dts =
b/arch/powerpc/boot/dts/p1023rds.dts
> index d9b7767..66bf804 100644
> --- a/arch/powerpc/boot/dts/p1023rds.dts
> +++ b/arch/powerpc/boot/dts/p1023rds.dts
> @@ -490,9 +490,9 @@
> 			interrupt-map-mask =3D <0xf800 0 0 7>;
> 			interrupt-map =3D <
> 				/* IDSEL 0x0 */
> -				0000 0 0 1 &mpic 4 1
> -				0000 0 0 2 &mpic 5 1
> -				0000 0 0 3 &mpic 6 1
> +				0000 0 0 1 &mpic 4 2
> +				0000 0 0 2 &mpic 5 2
> +				0000 0 0 3 &mpic 6 2
> 				0000 0 0 4 &mpic 7 1
> 				>;
> 			ranges =3D <0x2000000 0x0 0xa0000000
> @@ -532,7 +532,7 @@
> 				0000 0 0 1 &mpic 8 1
> 				0000 0 0 2 &mpic 9 1
> 				0000 0 0 3 &mpic 10 1
> -				0000 0 0 4 &mpic 11 1
> +				0000 0 0 4 &mpic 11 2
> 				>;
> 			ranges =3D <0x2000000 0x0 0x80000000
> 				  0x2000000 0x0 0x80000000
> --=20
> 1.6.0.6
>=20

Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Kumar Gala]

On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:

> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.
>=20
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> arch/powerpc/boot/dts/p1023rds.dts |    8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/powerpc/boot/dts/p1023rds.dts =
b/arch/powerpc/boot/dts/p1023rds.dts
> index d9b7767..66bf804 100644
> --- a/arch/powerpc/boot/dts/p1023rds.dts
> +++ b/arch/powerpc/boot/dts/p1023rds.dts
> @@ -490,9 +490,9 @@
> 			interrupt-map-mask =3D <0xf800 0 0 7>;
> 			interrupt-map =3D <
> 				/* IDSEL 0x0 */
> -				0000 0 0 1 &mpic 4 1
> -				0000 0 0 2 &mpic 5 1
> -				0000 0 0 3 &mpic 6 1
> +				0000 0 0 1 &mpic 4 2
> +				0000 0 0 2 &mpic 5 2
> +				0000 0 0 3 &mpic 6 2
> 				0000 0 0 4 &mpic 7 1
> 				>;
> 			ranges =3D <0x2000000 0x0 0xa0000000
> @@ -532,7 +532,7 @@
> 				0000 0 0 1 &mpic 8 1
> 				0000 0 0 2 &mpic 9 1
> 				0000 0 0 3 &mpic 10 1
> -				0000 0 0 4 &mpic 11 1
> +				0000 0 0 4 &mpic 11 2
> 				>;
> 			ranges =3D <0x2000000 0x0 0x80000000
> 				  0x2000000 0x0 0x80000000
> --=20
> 1.6.0.6
>=20

Should be setting ALL PCIe interrupts to '2'?  As I think in general we =
say these PCIe are 'active high'.  The only reason I would think we =
would NOT do this is if they are shared with some external device that =
is 'active low'.  If so we should comment that somewhere (maybe in the =
.dts, maybe just in the commit message).

- k

Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Scott Wood]

On 11/15/2011 03:51 PM, Kumar Gala wrote:
> 
> On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:
> 
> Should be setting ALL PCIe interrupts to '2'?  As I think in general
> we say these PCIe are 'active high'.  The only reason I would think
> we would NOT do this is if they are shared with some external device
> that is 'active low'.  If so we should comment that somewhere (maybe
> in the .dts, maybe just in the commit message).

I'd assume the ones that are pinned out are pulled high on the board.
Active-low is normal, it's these non-pinned-out "external" interrupts
that are pulled low inside the SoC that are weird.

-Scott

RE: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Zang Roy-R61911]

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, November 16, 2011 6:14 AM
> To: Kumar Gala
> Cc: Zang Roy-R61911; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level
> sensitive for PCIe
>=20
> On 11/15/2011 03:51 PM, Kumar Gala wrote:
> >
> > On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:
> >
> > Should be setting ALL PCIe interrupts to '2'?  As I think in general
> > we say these PCIe are 'active high'.  The only reason I would think
> > we would NOT do this is if they are shared with some external device
> > that is 'active low'.  If so we should comment that somewhere (maybe
> > in the .dts, maybe just in the commit message).
>=20
> I'd assume the ones that are pinned out are pulled high on the board.
yes. The boards pulled up the shared IRQs. PCIe specification does not spec=
ify 'active low' or 'active high', but for PCI, the INTx is 'active low'.

> Active-low is normal, it's these non-pinned-out "external" interrupts
> that are pulled low inside the SoC that are weird.
I agree here. Do you want me to add something to point out the "weird" in t=
he commit message?
Thanks.
Roy