Re: [PATCH] powerpc: Decode correct MSR bits in oops output

[Scott Wood <scottwood@freescale.com>]

On 11/28/2011 01:46 PM, Josh Boyer wrote:
> On Mon, Nov 28, 2011 at 2:30 PM, Scott Wood <scottwood@freescale.com> wrote:
>> On 11/28/2011 10:23 AM, Josh Boyer wrote:
>>> On Mon, Nov 28, 2011 at 11:04 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
>>>>
>>>> Since you're fixing this can you add the following for CONFIG_BOOKE:
>>>>
>>>> MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM

PMM is not just BookE, and is already present in the patch.

RI is present on e500mc (despite being reserved in book3e), so might not
want to stick that inside #ifndef CONFIG_BOOKE.

>> Not all bits are going to exist on all CPUs -- does 4xx use these bits
>> to mean something different?
> 
> No, marked as reserved.  However, given the patch shows up in human
> readable output, I don't think we want reserved bits being decoded and
> showing up inadvertently.

Do the bits ever actually get set on 4xx (documented or otherwise), or
is this a theoretical concern?

If 4xx must be excluded, use something like:
#if defined(CONFIG_BOOKE) && !defined(CONFIG_4xx)

Do we also need to patch out things like MSR_VEC at runtime, in case it
randomly shows up on a pre-Altivec CPU?

> Could introduce BOOK3E_32 to cover cases like this.

Why _32?  These bits apply to 64-bit as well.  MSR_CM is only for 64-bit.

UCLE and PMM are present on pre-2.06 e500 cores as well.

-Scott