* Multi-OS on P1022RDK Failing
@ 2011-12-07 14:57 Arshad, Farrukh
2011-12-07 21:24 ` Scott Wood
0 siblings, 1 reply; 4+ messages in thread
From: Arshad, Farrukh @ 2011-12-07 14:57 UTC (permalink / raw)
To: Linuxppc-dev@lists.ozlabs.org
[-- Attachment #1.1: Type: text/plain, Size: 3265 bytes --]
Greetings All,
I am trying to boot multi-OS on P1022RDK platform. As per my understating I only need to partition peripherals in DTS file of both kernels and configure memory start address of the kernel and load each kernel from uboot. No specific kernel configuration is required or any specific patch is required for this.
Given is my configuration
Core0: Linux kernel 1
Core1: Linux kernel 2
I compiled two different kernels with following configuration (rest is default for P1022RDK comes in LTIB)
Core 0 kernel
CONFIG_LOWMEM_SIZE = 0x10000000
CONFIG_PHYSICAL_START = 0x00000000
Core 1 kernel
CONFIG_LOWMEM_SIZE = 0x10000000
CONFIG_PHYSICAL_START = 0x10000000
In the DTS file I have partitioned peripherals & cpu to each kernel. Cpu 0 to Core 0 kernel & cpu 1 to Core 1 kernel and compiled DTS file with -b 1 switch of Core 1 DTB. My DTS files are attached. Given is my Uboot script which I am using to boot both cores.
-------------- Uboot load script -----------------
# General environment setting
setenv consoledev0 ttyS0
# Set kernel loading environment
setenv core1kernelbase 0x00000000
setenv core0kernelbase 0x10000000
setenv kernelsize 0x10000000
setenv kerneloffset 0x1000000
setenv fdtoffset 0x00c00000
setexpr load0addr $core0kernelbase + $kerneloffset
setexpr fdt0addr $core0kernelbase + $fdtoffset
setexpr load1addr $core1kernelbase + $kerneloffset
setexpr fdt1addr $core1kernelbase + $fdtoffset
setenv core0kernel uImage-custom-mel-p1022rdk-core0.bin
setenv core1kernel uImage-custom-ltib-p1022rdk-core1.bin
setenv core0fdt p1022rdk-core0.dtb
setenv core1fdt p1022rdk-core1.dtb
setenv core0rootfs /home/farshad/melfs/core0
setenv core1rootfs /home/farshad/melfs/core1
# Boot from NFS
setenv core0nfsbootargs root=/dev/nfs nfsroot=$serverip:/$core0rootfs ip=<dev_ip>::<nfs_server_ip>:::eth0:off rw debug console=$consoledev0,$baudrate maxcpus=1
setenv core1nfsbootargs root=/dev/nfs nfsroot=$serverip:/$core1rootfs ip=<dev_ip_2>::<nfs_server_ip>:::eth0:off rw debug console=$consoledev0,$baudrate maxcpus=1
echo == Transfer images on board ==
tftp $load0addr $core0kernel
tftp $fdt0addr $core0fdt
tftp $load1addr $core1kernel
tftp $fdt1addr $core1fdt
echo == Start loading Core 1 with LTIB Kernel ==
setenv bootm_low $core1kernelbase
setenv bootm_size $kernelsize
setenv bootargs $core1nfsbootargs
interrupts off
bootm start $load1addr - $fdt1addr
bootm loados
bootm fdt
fdt boardsetup
fdt chosen
bootm prep
cpu 1 release $load1addr - $fdt1addr -
echo == Start loading Core 0 with MEL Kernel ==
setenv bootargs $core0nfsbootargs
setenv bootm_low $core0kernelbase
setenv bootm_size $kernelsize
bootm $load0addr - $fdt0addr
-------------- Uboot load script ends -----------------
My problem is Core 0 kernel is booting successfully but Core 1 kernel hangs after uncompressing kernel image, and after that I don't see anything on the console.
Any thoughts on what I am missing or doing incorrect?
Best Regards
Farrukh Arshad
Sr. Software Development Engineer
Mentor Graphics Pakistan
Ph: +92 - 423 - 609 - 92 - 09
Cell: +92 - 303 - 444 - 77 - 05
[-- Attachment #1.2: Type: text/html, Size: 12063 bytes --]
[-- Attachment #2: p1022rdk-core0.dts --]
[-- Type: application/octet-stream, Size: 15610 bytes --]
/*
* P1022 RDK - Core 0 Device Tree Source
*
*/
/dts-v1/;
/ {
model = "fsl,P1022";
compatible = "fsl,P1022DS";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet0;
serial0 = &serial1;
msgr-block0 = &msgr_block0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1022@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
mcomm {
compatible = "ment,mcomm";
//reg = <0 0x70000000 0 0x10000000>;
//reg = <0 0x18000000 0 0x080000000>;
reg = <0 0x18000000 0 0x008000000>;
notifications = <
1 1 // Core 1, Msg Reg 1
0 0 // Core 0, Msg Reg 0
>;
};
//localbus@ffe05000 {
// #address-cells = <2>;
// #size-cells = <1>;
// compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
// reg = <0 0xffe05000 0 0x1000>;
// interrupts = <19 2>;
// interrupt-parent = <&mpic>;
// ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
// 0x1 0x0 0x0 0xe0000000 0x08000000
// 0x2 0x0 0x0 0xffa00000 0x00040000
// 0x3 0x0 0x0 0xffdf0000 0x00008000>;
// nor@0,0 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "cfi-flash";
// reg = <0x0 0x0 0x8000000>;
// bank-width = <2>;
// device-width = <1>;
// partition@0 {
// reg = <0x0 0x03000000>;
// label = "ramdisk-nor";
// read-only;
// };
// partition@3000000 {
// reg = <0x03000000 0x00e00000>;
// label = "diagnostic-nor";
// read-only;
// };
// partition@3e00000 {
// reg = <0x03e00000 0x00200000>;
// label = "dink-nor";
// read-only;
// };
// partition@4000000 {
// reg = <0x04000000 0x00400000>;
// label = "kernel-nor";
// read-only;
// };
// partition@4400000 {
// reg = <0x04400000 0x03b00000>;
// label = "jffs2-nor";
// };
// partition@7f00000 {
// reg = <0x07f00000 0x00080000>;
// label = "dtb-nor";
// read-only;
// };
// partition@7f80000 {
// reg = <0x07f80000 0x00080000>;
// label = "u-boot-nor";
// read-only;
// };
// };
// nand@2,0 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "fsl,elbc-fcm-nand";
// reg = <0x2 0x0 0x40000>;
// partition@0 {
// reg = <0x0 0x02000000>;
// label = "u-boot-nand";
// read-only;
// };
// partition@2000000 {
// reg = <0x02000000 0x10000000>;
// label = "jffs2-nand";
// };
// partition@12000000 {
// reg = <0x12000000 0x10000000>;
// label = "ramdisk-nand";
// read-only;
// };
// partition@22000000 {
// reg = <0x22000000 0x04000000>;
// label = "kernel-nand";
// };
// partition@26000000 {
// reg = <0x26000000 0x01000000>;
// label = "dtb-nand";
// read-only;
// };
// partition@27000000 {
// reg = <0x27000000 0x19000000>;
// label = "reserved-nand";
// };
// };
//};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1022-immr", "simple-bus";
ranges = <0x0 0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
//ecm-law@0 {
// compatible = "fsl,ecm-law";
// reg = <0x0 0x1000>;
// fsl,num-laws = <12>;
//};
//ecm@1000 {
// compatible = "fsl,p1022-ecm", "fsl,ecm";
// reg = <0x1000 0x1000>;
// interrupts = <16 2>;
// interrupt-parent = <&mpic>;
//};
//memory-controller@2000 {
// compatible = "fsl,p1022-memory-controller";
// reg = <0x2000 0x1000>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
//};
//i2c@3000 {
// #address-cells = <1>;
// #size-cells = <0>;
// cell-index = <0>;
// compatible = "fsl-i2c";
// reg = <0x3000 0x100>;
// interrupts = <43 2>;
// interrupt-parent = <&mpic>;
// dfsrr;
//};
//ssi@15000 {
// compatible = "fsl,p1022-ssi";
// cell-index = <0>;
// reg = <0x15000 0x100>;
// interrupt-parent = <&mpic>;
// interrupts = <75 2>;
// fsl,mode = "i2s-slave";
// codec-handle = <&wm8776>;
// fsl,playback-dma = <&dma00>;
// fsl,capture-dma = <&dma01>;
// fsl,fifo-depth = <15>;
// fsl,ssi-asynchronous = <1>;
//};
//i2c@3100 {
// #address-cells = <1>;
// #size-cells = <0>;
// cell-index = <1>;
// compatible = "fsl-i2c";
// reg = <0x3100 0x100>;
// interrupts = <43 2>;
// interrupt-parent = <&mpic>;
// dfsrr;
// rtc@68{
// compatible = "dallas,ds3232";
// reg = <0x68>;
// interrupts = <16 0x2>;
// interrupt-parent = <&mpic>;
// };
// adt7461@4c{
// compatible = "adi,adt7461";
// reg = <0x4c>;
// };
// zl6100@21{
// compatible = "intersil,zl6100";
// reg = <0x21>;
// };
// zl6100@24{
// compatible = "intersil,zl6100";
// reg = <0x24>;
// };
// zl6100@26{
// compatible = "intersil,zl6100";
// reg = <0x26>;
// };
// zl6100@29{
// compatible = "intersil,zl6100";
// reg = <0x29>;
// };
// wm8776:codec@1a {
// compatible = "wolfson,wm8776";
// reg = <0x1a>;
// clock-frequency = <0xbb8000>;
// };
//};
//serial0: serial@4500 {
// cell-index = <0>;
// device_type = "serial";
// compatible = "ns16550";
// reg = <0x4500 0x100>;
// clock-frequency = <0>;
// interrupts = <42 2>;
// interrupt-parent = <&mpic>;
//};
serial1: serial@4600 {
cell-index = <1>;
device-type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
//spi@7000 {
// cell-index = <0>;
// #address-cells = <1>;
// #size-cells = <0>;
// compatible = "fsl,espi";
// reg = <0x7000 0x1000>;
// interrupts = <59 0x2>;
// interrupt-parent = <&mpic>;
// espi,num-ss-bits = <4>;
// mode = "cpu";
// fsl_m25p80@0 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "fsl,espi-flash";
// reg = <0>;
// linux,modalias = "fsl_m25p80";
// spi-max-frequency = <40000000>; /* input clock */
// partition@0 {
// label = "u-boot-spi";
// reg = <0x00000000 0x00100000>;
// read-only;
// };
// partition@100000 {
// label = "kernel-spi";
// reg = <0x00100000 0x00500000>;
// read-only;
// };
// partition@600000 {
// label = "dtb-spi";
// reg = <0x00600000 0x00100000>;
// read-only;
// };
// partition@700000 {
// label = "file system-spi";
// reg = <0x00700000 0x00900000>;
// };
// };
//};
//gpio: gpio-controller@f000 {
// #gpio-cells = <2>;
// compatible = "fsl,mpc8572-gpio";
// reg = <0xf000 0x100>;
// interrupts = <47 0x2>;
// interrupt-parent = <&mpic>;
// gpio-controller;
//};
L2: l2-cache-controller@20000 {
compatible = "fsl,p1022-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
//dma@21300 {
// #address-cells = <1>;
// #size-cells = <1>;
// compatible = "fsl,eloplus-dma";
// reg = <0x21300 0x4>;
// ranges = <0x0 0x21100 0x200>;
// cell-index = <0>;
// dma00: dma-channel@0 {
// compatible = "fsl,ssi-dma-channel";
// reg = <0x0 0x80>;
// cell-index = <0>;
// interrupt-parent = <&mpic>;
// interrupts = <20 2>;
// };
// dma01: dma-channel@80 {
// compatible = "fsl,ssi-dma-channel";
// reg = <0x80 0x80>;
// cell-index = <1>;
// interrupt-parent = <&mpic>;
// interrupts = <21 2>;
// };
// dma-channel@100 {
// compatible = "fsl,eloplus-dma-channel";
// reg = <0x100 0x80>;
// cell-index = <2>;
// interrupt-parent = <&mpic>;
// interrupts = <22 2>;
// };
// dma-channel@180 {
// compatible = "fsl,eloplus-dma-channel";
// reg = <0x180 0x80>;
// cell-index = <3>;
// interrupt-parent = <&mpic>;
// interrupts = <23 2>;
// };
//};
//usb@22000 {
// #address-cells = <1>;
// #size-cells = <0>;
// compatible = "fsl-usb2-dr";
// reg = <0x22000 0x1000>;
// interrupt-parent = <&mpic>;
// interrupts = <28 0x2>;
// phy_type = "ulpi";
//};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupts = <3 1>;
reg = <0x1>;
};
//phy1: ethernet-phy@1 {
// interrupts = <9 1>;
// reg = <0x2>;
//};
};
//mdio@25000 {
// #address-cells = <1>;
// #size-cells = <0>;
// compatible = "fsl,etsec2-mdio";
// reg = <0x25000 0x1000 0xb1030 0x4>;
//};
enet0: ethernet@B0000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
fsl,wake-on-filer;
clk-handle = <&etsec1_clk>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB0000 0x1000>;
interrupts = <29 2 30 2 34 2>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB4000 0x1000>;
interrupts = <17 2 18 2 24 2>;
};
};
//sdhci@2e000 {
// compatible = "fsl,p1022-esdhc", "fsl,esdhc";
// reg = <0x2e000 0x1000>;
// interrupts = <72 0x2>;
// interrupt-parent = <&mpic>;
// fsl,sdhci-auto-cmd12;
// /* Filled in by U-Boot */
// clock-frequency = <0>;
//};
//crypto@30000 {
// compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
// "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
// reg = <0x30000 0x10000>;
// interrupts = <45 2 58 2>;
// interrupt-parent = <&mpic>;
// fsl,num-channels = <4>;
// fsl,channel-fifo-len = <24>;
// fsl,exec-units-mask = <0xbfe>;
// fsl,descriptor-types-mask = <0x3ab0ebf>;
// fsl,multi-host-mode = "primary";
// fsl,channel-remap = <0x3>;
//};
//sata@18000 {
// compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
// reg = <0x18000 0x1000>;
// cell-index = <1>;
// interrupts = <74 0x2>;
// interrupt-parent = <&mpic>;
//};
//sata@19000 {
// compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
// reg = <0x19000 0x1000>;
// cell-index = <2>;
// interrupts = <41 0x2>;
// interrupt-parent = <&mpic>;
//};
//display@10000 {
// compatible = "fsl,diu", "fsl,p1022-diu";
// reg = <0x10000 1000>;
// interrupts = <64 2>;
// interrupt-parent = <&mpic>;
//};
power@e0070{
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
"fsl,p1022-pmc";
reg = <0xe0070 0x20>;
etsec1_clk: soc-clk@B0{
fsl,pmcdr-mask = <0x00000080>;
};
etsec2_clk: soc-clk@B1{
fsl,pmcdr-mask = <0x00000040>;
};
};
//timer@41100 {
// compatible = "fsl,mpic-global-timer";
// reg = <0x41100 0x204>;
// interrupts = <0xf7 0x2>;
// interrupt-parent = <&mpic>;
//};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
pic-no-reset;
protected-sources = <
19 // localbus@ffe0500
42 // serial@4600
16 // ecm@1000
// memory-controller@20000
// rtc@68
43 // i2c@3000, i2c@3100
75 // ssi@15000
59 // spi@7000
47 // gpio@f000
20 // dma-channel@0
21 // dma-channel@80
22 // dma-channel@100
23 // dma-channel@180
28 // usb@22000
9 // ethernet-phy@1
35 36 40 // queue-group@0
51 52 67 // queue-group@1
58 // crypto@30000
41 // sata@19000
74 // sata@18000
64 // display@10000
0xF7 // timer@41100
0xb1 // message@41400
16 // pci@ffe09000
// pci@ffe0a000
// pci@ffe0b000
0xe0 0xe1 0xe2 0xe3 // msi@41600
>;
};
msgr_block0: message@41400 {
compatible = "fsl,p1022-msg","fsl,mpic-msg",
"fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
cell-index = <1>;
interrupts = <0xb0 2 0xb2 2 0xb3 2>;
msg-receive-mask = <0xd>;
interrupt-parent = < &mpic >;
};
//msgr_block0: message@41400 {
// compatible = "fsl,p1022-msg","fsl,mpic-msg",
// "fsl,mpic-v3.1-msgr";
// reg = <0x41400 0x200>;
// interrupts = <0xb0 0x2 0xb1 0x2 0xb2 0x2 0xb3 2>;
// interrupt-parent = < &mpic >;
//};
//msi@41600 {
// compatible = "fsl,mpic-msi";
// reg = <0x41600 0x80>;
// msi-available-ranges = <0 0x100>;
// interrupts = <
// 0xe0 0
// 0xe1 0
// 0xe2 0
// 0xe3 0
// 0xe4 0
// 0xe5 0
// 0xe6 0
// 0xe7 0>;
// interrupt-parent = <&mpic>;
//};
//global-utilities@e0000 { //global utilities block
// compatible = "fsl,p1022-guts";
// reg = <0xe0000 0x1000>;
// fsl,has-rstcr;
//};
};
//pci0: pcie@ffe09000 {
// cell-index = <2>;
// compatible = "fsl,p1022-pcie";
// device_type = "pci";
// #interrupt-cells = <1>;
// #size-cells = <2>;
// #address-cells = <3>;
// reg = <0 0xffe09000 0 0x1000>;
// bus-range = <0 255>;
// ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
// 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
// clock-frequency = <33333333>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
// interrupt-map-mask = <0xf800 0 0 7>;
// interrupt-map = <
// /* IDSEL 0x0 */
// 0000 0 0 1 &mpic 4 1
// 0000 0 0 2 &mpic 5 1
// 0000 0 0 3 &mpic 6 1
// 0000 0 0 4 &mpic 7 1
// >;
// pcie@0 {
// reg = <0x0 0x0 0x0 0x0 0x0>;
// #size-cells = <2>;
// #address-cells = <3>;
// device_type = "pci";
// ranges = <0x2000000 0x0 0xa0000000
// 0x2000000 0x0 0xa0000000
// 0x0 0x20000000
// 0x1000000 0x0 0x0
// 0x1000000 0x0 0x0
// 0x0 0x100000>;
// };
//};
//pci1: pcie@ffe0a000 {
// cell-index = <1>;
// compatible = "fsl,p1022-pcie";
// device_type = "pci";
// #interrupt-cells = <1>;
// #size-cells = <2>;
// #address-cells = <3>;
// reg = <0 0xffe0a000 0 0x1000>;
// bus-range = <0 255>;
// ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
// 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
// clock-frequency = <33333333>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
// interrupt-map-mask = <0xf800 0 0 7>;
// interrupt-map = <
// /* IDSEL 0x0 */
// 0000 0 0 1 &mpic 0 1
// 0000 0 0 2 &mpic 1 1
// 0000 0 0 3 &mpic 2 1
// 0000 0 0 4 &mpic 3 1
// >;
// pcie@0 {
// reg = <0x0 0x0 0x0 0x0 0x0>;
// #size-cells = <2>;
// #address-cells = <3>;
// device_type = "pci";
// ranges = <0x2000000 0x0 0xc0000000
// 0x2000000 0x0 0xc0000000
// 0x0 0x20000000
// 0x1000000 0x0 0x0
// 0x1000000 0x0 0x0
// 0x0 0x100000>;
// };
//};
//pci2: pcie@ffe0b000 {
// cell-index = <3>;
// compatible = "fsl,p1022-pcie";
// device_type = "pci";
// #interrupt-cells = <1>;
// #size-cells = <2>;
// #address-cells = <3>;
// reg = <0 0xffe0b000 0 0x1000>;
// bus-range = <0 255>;
// ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
// 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
// clock-frequency = <33333333>;
// interrupt-parent = <&mpic>;
// interrupts = <16 2>;
// interrupt-map-mask = <0xf800 0 0 7>;
// interrupt-map = <
// /* IDSEL 0x0 */
// 0000 0 0 1 &mpic 8 1
// 0000 0 0 2 &mpic 9 1
// 0000 0 0 3 &mpic 10 1
// 0000 0 0 4 &mpic 11 1
// >;
// pcie@0 {
// reg = <0x0 0x0 0x0 0x0 0x0>;
// #size-cells = <2>;
// #address-cells = <3>;
// device_type = "pci";
// ranges = <0x2000000 0x0 0x80000000
// 0x2000000 0x0 0x80000000
// 0x0 0x20000000
// 0x1000000 0x0 0x0
// 0x1000000 0x0 0x0
// 0x0 0x100000>;
// };
//};
};
[-- Attachment #3: p1022rdk-core1.dts --]
[-- Type: application/octet-stream, Size: 15964 bytes --]
/*
* P1022 RDK - Core 1 Device Tree Source
*
*/
/dts-v1/;
/ {
model = "fsl,P1022";
compatible = "fsl,P1022DS";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet1 = &enet1;
serial0 = &serial0;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
//PowerPC,P1022@0 {
// device_type = "cpu";
// reg = <0x0>;
// next-level-cache = <&L2>;
//};
PowerPC,P1022@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
0x1 0x0 0x0 0xe0000000 0x08000000
0x2 0x0 0x0 0xffa00000 0x00040000
0x3 0x0 0x0 0xffdf0000 0x00008000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
reg = <0x0 0x03000000>;
label = "ramdisk-nor";
read-only;
};
partition@3000000 {
reg = <0x03000000 0x00e00000>;
label = "diagnostic-nor";
read-only;
};
partition@3e00000 {
reg = <0x03e00000 0x00200000>;
label = "dink-nor";
read-only;
};
partition@4000000 {
reg = <0x04000000 0x00400000>;
label = "kernel-nor";
read-only;
};
partition@4400000 {
reg = <0x04400000 0x03b00000>;
label = "jffs2-nor";
};
partition@7f00000 {
reg = <0x07f00000 0x00080000>;
label = "dtb-nor";
read-only;
};
partition@7f80000 {
reg = <0x07f80000 0x00080000>;
label = "u-boot-nor";
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
partition@0 {
reg = <0x0 0x02000000>;
label = "u-boot-nand";
read-only;
};
partition@2000000 {
reg = <0x02000000 0x10000000>;
label = "jffs2-nand";
};
partition@12000000 {
reg = <0x12000000 0x10000000>;
label = "ramdisk-nand";
read-only;
};
partition@22000000 {
reg = <0x22000000 0x04000000>;
label = "kernel-nand";
};
partition@26000000 {
reg = <0x26000000 0x01000000>;
label = "dtb-nand";
read-only;
};
partition@27000000 {
reg = <0x27000000 0x19000000>;
label = "reserved-nand";
};
};
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1022-immr", "simple-bus";
ranges = <0x0 0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p1022-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p1022-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
ssi@15000 {
compatible = "fsl,p1022-ssi";
cell-index = <0>;
reg = <0x15000 0x100>;
interrupt-parent = <&mpic>;
interrupts = <75 2>;
fsl,mode = "i2s-slave";
codec-handle = <&wm8960>;
fsl,playback-dma = <&dma00>;
fsl,capture-dma = <&dma01>;
fsl,fifo-depth = <15>;
fsl,ssi-asynchronous = <1>;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68{
compatible = "dallas,ds3232";
reg = <0x68>;
interrupts = <16 0x2>;
interrupt-parent = <&mpic>;
};
adt7461@4c{
compatible = "adi,adt7461";
reg = <0x4c>;
};
zl6100@21{
compatible = "intersil,zl6100";
reg = <0x21>;
};
zl6100@24{
compatible = "intersil,zl6100";
reg = <0x24>;
};
zl6100@26{
compatible = "intersil,zl6100";
reg = <0x26>;
};
zl6100@29{
compatible = "intersil,zl6100";
reg = <0x29>;
};
wm8960:codec@1a {
compatible = "wolfson,wm8960";
reg = <0x1a>;
clock-frequency = <0xbb8000>;
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
//serial1: serial@4600 {
// cell-index = <1>;
// device_type = "serial";
// compatible = "ns16550";
// reg = <0x4600 0x100>;
// clock-frequency = <0>;
// interrupts = <42 2>;
// interrupt-parent = <&mpic>;
//};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
espi,num-ss-bits = <4>;
mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,espi-flash";
reg = <0>;
linux,modalias = "fsl_m25p80";
spi-max-frequency = <40000000>; /* input clock */
partition@0 {
label = "u-boot-spi";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@100000 {
label = "kernel-spi";
reg = <0x00100000 0x00500000>;
read-only;
};
partition@600000 {
label = "dtb-spi";
reg = <0x00600000 0x00100000>;
read-only;
};
partition@700000 {
label = "file system-spi";
reg = <0x00700000 0x00900000>;
};
};
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p1022-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
//interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma00: dma-channel@0 {
compatible = "fsl,ssi-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma01: dma-channel@80 {
compatible = "fsl,ssi-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
phy_type = "ulpi";
};
usb@23000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <46 0x2>;
phy_type = "ulpi";
};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
//phy0: ethernet-phy@0 {
// interrupt-parent = <&mpic>;
// interrupts = <3 1>;
// reg = <0x1>;
//};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <9 1>;
reg = <0x2>;
};
};
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x25000 0x1000 0xb1030 0x4>;
};
//enet0: ethernet@B0000 {
// #address-cells = <1>;
// #size-cells = <1>;
// cell-index = <0>;
// device_type = "network";
// model = "eTSEC";
// compatible = "fsl,etsec2";
// fsl,num_rx_queues = <0x8>;
// fsl,num_tx_queues = <0x8>;
// fsl,magic-packet;
// fsl,wake-on-filer;
// clk-handle = <&etsec1_clk>;
// local-mac-address = [ 00 00 00 00 00 00 ];
// interrupt-parent = <&mpic>;
// fixed-link = <1 1 1000 0 0>;
// phy-handle = <&phy0>;
// phy-connection-type = "rgmii-id";
// queue-group@0{
// #address-cells = <1>;
// #size-cells = <1>;
// reg = <0xB0000 0x1000>;
// interrupts = <29 2 30 2 34 2>;
// };
// queue-group@1{
// #address-cells = <1>;
// #size-cells = <1>;
// reg = <0xB4000 0x1000>;
// interrupts = <17 2 18 2 24 2>;
// };
//};
enet1: ethernet@B1000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
clk-handle = <&etsec2_clk>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB1000 0x1000>;
interrupts = <35 2 36 2 40 2>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB5000 0x1000>;
interrupts = <51 2 52 2 67 2>;
};
};
sdhci@2e000 {
compatible = "fsl,p1022-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
fsl,sdhci-auto-cmd12;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
"fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3a30abf>;
// fsl,multi-host-mode = "dual";
fsl,channel-remap = <0x3>;
};
sata@18000 {
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <1>;
interrupts = <74 0x2>;
interrupt-parent = <&mpic>;
};
sata@19000 {
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <2>;
interrupts = <41 0x2>;
interrupt-parent = <&mpic>;
};
display@10000 {
compatible = "fsl,diu", "fsl,p1022-diu";
reg = <0x10000 1000>;
interrupts = <64 2>;
interrupt-parent = <&mpic>;
};
power@e0070{
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
"fsl,p1022-pmc";
reg = <0xe0070 0x20>;
etsec1_clk: soc-clk@B0{
fsl,pmcdr-mask = <0x00000080>;
};
etsec2_clk: soc-clk@B1{
fsl,pmcdr-mask = <0x00000040>;
};
};
timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x204>;
interrupts = <0xf7 0x2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
//compatible = "fsl,mpic";
device_type = "open-pic";
pic-no-reset;
protected-sources = <
16 // l2-cache-controller@20000
3 // ethernet-phy@0
29 30 34 // queue-group@0
17 18 24 // gueue-group@1
42 // serial@4500
>;
};
message@41400 {
compatible = "fsl,p1022-msg","fsl,mpic-msg";
reg = <0x41400 0x200>;
cell-index = <1>;
interrupts = <0xb0 2 0xb1 2 0xb2 2 0xb3 2>;
interrupt-parent = < &mpic >;
};
message@42400 {
compatible = "fsl,p1022-msg","fsl,mpic-msg";
reg = <0x42400 0x200>;
cell-index = <2>;
interrupts = <0xb4 2 0xb5 2 0xb6 2 0xb7 2>;
interrupt-parent = < &mpic >;
};
msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,p1022-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@ffe09000 {
cell-index = <2>;
compatible = "fsl,p1022-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
cell-index = <1>;
compatible = "fsl,p1022-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci2: pcie@ffe0b000 {
cell-index = <3>;
compatible = "fsl,p1022-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0b000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 8 1
0000 0 0 2 &mpic 9 1
0000 0 0 3 &mpic 10 1
0000 0 0 4 &mpic 11 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: Multi-OS on P1022RDK Failing 2011-12-07 14:57 Multi-OS on P1022RDK Failing Arshad, Farrukh @ 2011-12-07 21:24 ` Scott Wood 2011-12-08 6:35 ` Arshad, Farrukh 2011-12-08 15:24 ` Arshad, Farrukh 0 siblings, 2 replies; 4+ messages in thread From: Scott Wood @ 2011-12-07 21:24 UTC (permalink / raw) To: Arshad, Farrukh; +Cc: Linuxppc-dev@lists.ozlabs.org On 12/07/2011 08:57 AM, Arshad, Farrukh wrote: > Core 0 kernel >=20 > CONFIG_LOWMEM_SIZE =3D 0x10000000 >=20 > CONFIG_PHYSICAL_START =3D 0x00000000 >=20 > =20 >=20 > Core 1 kernel >=20 > CONFIG_LOWMEM_SIZE =3D 0x10000000 >=20 > CONFIG_PHYSICAL_START =3D 0x10000000 Why are you messing with CONFIG_LOWMEM_SIZE? That adjusts the lowmem/highmem split, not the total amount of memory that this instance of Linux will use (though you may get that behavior as a side effect if highmem is disabled). U-boot should set the memory node in the device tree based on the bootm_low/bootm_size environment variables. > # Boot from NFS >=20 > setenv core0nfsbootargs root=3D/dev/nfs nfsroot=3D$serverip:/$core0root= fs > ip=3D<dev_ip>::<nfs_server_ip>:::eth0:off rw debug > console=3D$consoledev0,$baudrate maxcpus=3D1 >=20 > setenv core1nfsbootargs root=3D/dev/nfs nfsroot=3D$serverip:/$core1root= fs > ip=3D<dev_ip_2>::<nfs_server_ip>:::eth0:off rw debug > console=3D$consoledev0,$baudrate maxcpus=3D1 maxcpus should be unnecessary -- there will only be one cpu in the device tree for each partition. > My problem is Core 0 kernel is booting successfully but Core 1 kernel > hangs after uncompressing kernel image, and after that I don=92t see > anything on the console. >=20 > =20 >=20 > Any thoughts on what I am missing or doing incorrect? The "cpu 1 release" command should be using the address of the decompressed kernel (should be $bootm_low), not where the uImage was load= ed. Also, the two serial ports you're using share an interrupt -- this shouldn't stop kernel message output, but it's going to be a problem for userspace usage of the port. You should remove the interrupts property from the serial node in both partitions, so Linux will poll instead. -Scott ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: Multi-OS on P1022RDK Failing 2011-12-07 21:24 ` Scott Wood @ 2011-12-08 6:35 ` Arshad, Farrukh 2011-12-08 15:24 ` Arshad, Farrukh 1 sibling, 0 replies; 4+ messages in thread From: Arshad, Farrukh @ 2011-12-08 6:35 UTC (permalink / raw) To: Scott Wood; +Cc: Linuxppc-dev@lists.ozlabs.org Thanks Scott.=20 Fixing cpu 1 release address solved my problem. Also thanks for the CONFIG_= LOWMEM_SIZE suggestions. Regards, Farrukh Arshad -----Original Message----- From: Scott Wood [mailto:scottwood@freescale.com]=20 Sent: Thursday, December 08, 2011 2:24 AM To: Arshad, Farrukh Cc: Linuxppc-dev@lists.ozlabs.org Subject: Re: Multi-OS on P1022RDK Failing On 12/07/2011 08:57 AM, Arshad, Farrukh wrote: > Core 0 kernel >=20 > CONFIG_LOWMEM_SIZE =3D 0x10000000 >=20 > CONFIG_PHYSICAL_START =3D 0x00000000 >=20 > =20 >=20 > Core 1 kernel >=20 > CONFIG_LOWMEM_SIZE =3D 0x10000000 >=20 > CONFIG_PHYSICAL_START =3D 0x10000000 Why are you messing with CONFIG_LOWMEM_SIZE? That adjusts the lowmem/highm= em split, not the total amount of memory that this instance of Linux will u= se (though you may get that behavior as a side effect if highmem is disable= d). U-boot should set the memory node in the device tree based on the boot= m_low/bootm_size environment variables. > # Boot from NFS >=20 > setenv core0nfsbootargs root=3D/dev/nfs nfsroot=3D$serverip:/$core0rootfs= =20 > ip=3D<dev_ip>::<nfs_server_ip>:::eth0:off rw debug=20 > console=3D$consoledev0,$baudrate maxcpus=3D1 >=20 > setenv core1nfsbootargs root=3D/dev/nfs nfsroot=3D$serverip:/$core1rootfs= =20 > ip=3D<dev_ip_2>::<nfs_server_ip>:::eth0:off rw debug=20 > console=3D$consoledev0,$baudrate maxcpus=3D1 maxcpus should be unnecessary -- there will only be one cpu in the device t= ree for each partition. > My problem is Core 0 kernel is booting successfully but Core 1 kernel=20 > hangs after uncompressing kernel image, and after that I don't see=20 > anything on the console. >=20 > =20 >=20 > Any thoughts on what I am missing or doing incorrect? The "cpu 1 release" command should be using the address of the decompressed= kernel (should be $bootm_low), not where the uImage was loaded. Also, the two serial ports you're using share an interrupt -- this shouldn'= t stop kernel message output, but it's going to be a problem for userspace = usage of the port. You should remove the interrupts property from the seri= al node in both partitions, so Linux will poll instead. -Scott ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: Multi-OS on P1022RDK Failing 2011-12-07 21:24 ` Scott Wood 2011-12-08 6:35 ` Arshad, Farrukh @ 2011-12-08 15:24 ` Arshad, Farrukh 1 sibling, 0 replies; 4+ messages in thread From: Arshad, Farrukh @ 2011-12-08 15:24 UTC (permalink / raw) To: Scott Wood; +Cc: linuxppc-dev@lists.ozlabs.org [-- Attachment #1: Type: text/plain, Size: 3892 bytes --] Just a quick question, For Core 1 I am booting kernel using NFS. When I boot kernel on Core 1 it fails at following point. Attached are my DTS files for both cores. My NFS server is configured properly as I am booting Core 0 with the same server. I have used packet sniffer on my NFS server and I see no packet from Core 1 for my NFS server. Do you think this is problem in my DTS file or kernel configuration. Any help is appreciated. ........................ [ 88.940597] rxbd[5]: addr,vaddr=0xf777400,0xcf777400 [ 88.945561] rxbd[6]: addr,vaddr=0xf777800,0xcf777800 [ 88.950526] rxbd[7]: addr,vaddr=0xf777c00,0xcf777c00 OK [ 89.873634] ----PHY: skipping MII_CTRL1000 write. [ 89.957631] IP-Config: Guessing netmask 255.255.0.0 [ 89.962653] IP-Config: Complete: [ 89.965724] device=eth0, addr=<ip_address>, mask=255.255.0.0, gw=<gateway_ip>, [ 89.973843] host=<host_ip>, domain=, nis-domain=(none), [ 89.980025] bootserver=255.255.255.255, rootserver=<nfs_server_ip>, rootpath= [ 89.988012] Looking up port of RPC 100003/2 on 137.202.156.191 [ 90.877650] PHY: 0:01 - Link is Up - 1000/Full [ 124.993637] rpcbind: server <nfs_server_ip> not responding, timed out [ 125.000136] Root-NFS: Unable to get nfsd port number from server, using default [ 125.007458] Looking up port of RPC 100005/1 on <nfs_server_ip> [ 160.009636] rpcbind: server 137.202.156.191 not responding, timed out [ 160.016131] Root-NFS: Unable to get mountd port number from server, using default Regards, Farrukh Arshad -----Original Message----- From: Arshad, Farrukh Sent: Thursday, December 08, 2011 11:35 AM To: 'Scott Wood' Cc: Linuxppc-dev@lists.ozlabs.org Subject: RE: Multi-OS on P1022RDK Failing Thanks Scott. Fixing cpu 1 release address solved my problem. Also thanks for the CONFIG_LOWMEM_SIZE suggestions. Regards, Farrukh Arshad -----Original Message----- From: Scott Wood [mailto:scottwood@freescale.com] Sent: Thursday, December 08, 2011 2:24 AM To: Arshad, Farrukh Cc: Linuxppc-dev@lists.ozlabs.org Subject: Re: Multi-OS on P1022RDK Failing On 12/07/2011 08:57 AM, Arshad, Farrukh wrote: > Core 0 kernel > > CONFIG_LOWMEM_SIZE = 0x10000000 > > CONFIG_PHYSICAL_START = 0x00000000 > > > > Core 1 kernel > > CONFIG_LOWMEM_SIZE = 0x10000000 > > CONFIG_PHYSICAL_START = 0x10000000 Why are you messing with CONFIG_LOWMEM_SIZE? That adjusts the lowmem/highmem split, not the total amount of memory that this instance of Linux will use (though you may get that behavior as a side effect if highmem is disabled). U-boot should set the memory node in the device tree based on the bootm_low/bootm_size environment variables. > # Boot from NFS > > setenv core0nfsbootargs root=/dev/nfs nfsroot=$serverip:/$core0rootfs > ip=<dev_ip>::<nfs_server_ip>:::eth0:off rw debug > console=$consoledev0,$baudrate maxcpus=1 > > setenv core1nfsbootargs root=/dev/nfs nfsroot=$serverip:/$core1rootfs > ip=<dev_ip_2>::<nfs_server_ip>:::eth0:off rw debug > console=$consoledev0,$baudrate maxcpus=1 maxcpus should be unnecessary -- there will only be one cpu in the device tree for each partition. > My problem is Core 0 kernel is booting successfully but Core 1 kernel > hangs after uncompressing kernel image, and after that I don't see > anything on the console. > > > > Any thoughts on what I am missing or doing incorrect? The "cpu 1 release" command should be using the address of the decompressed kernel (should be $bootm_low), not where the uImage was loaded. Also, the two serial ports you're using share an interrupt -- this shouldn't stop kernel message output, but it's going to be a problem for userspace usage of the port. You should remove the interrupts property from the serial node in both partitions, so Linux will poll instead. -Scott [-- Attachment #2: p1022rdk-core1.dts --] [-- Type: application/octet-stream, Size: 16183 bytes --] /* * P1022 RDK - Core 1 Device Tree Source * */ /dts-v1/; / { model = "fsl,P1022"; compatible = "fsl,P1022DS"; #address-cells = <2>; #size-cells = <2>; aliases { ethernet1 = &enet1; serial0 = &serial0; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; }; cpus { #address-cells = <1>; #size-cells = <0>; //PowerPC,P1022@0 { // device_type = "cpu"; // reg = <0x0>; // next-level-cache = <&L2>; //}; PowerPC,P1022@1 { device_type = "cpu"; reg = <0x1>; next-level-cache = <&L2>; }; }; memory { device_type = "memory"; }; localbus@ffe05000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; reg = <0 0xffe05000 0 0x1000>; interrupts = <19 2>; interrupt-parent = <&mpic>; ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 0x1 0x0 0x0 0xe0000000 0x08000000 0x2 0x0 0x0 0xffa00000 0x00040000 0x3 0x0 0x0 0xffdf0000 0x00008000>; nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; bank-width = <2>; device-width = <1>; partition@0 { reg = <0x0 0x03000000>; label = "ramdisk-nor"; read-only; }; partition@3000000 { reg = <0x03000000 0x00e00000>; label = "diagnostic-nor"; read-only; }; partition@3e00000 { reg = <0x03e00000 0x00200000>; label = "dink-nor"; read-only; }; partition@4000000 { reg = <0x04000000 0x00400000>; label = "kernel-nor"; read-only; }; partition@4400000 { reg = <0x04400000 0x03b00000>; label = "jffs2-nor"; }; partition@7f00000 { reg = <0x07f00000 0x00080000>; label = "dtb-nor"; read-only; }; partition@7f80000 { reg = <0x07f80000 0x00080000>; label = "u-boot-nor"; read-only; }; }; nand@2,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,elbc-fcm-nand"; reg = <0x2 0x0 0x40000>; partition@0 { reg = <0x0 0x02000000>; label = "u-boot-nand"; read-only; }; partition@2000000 { reg = <0x02000000 0x10000000>; label = "jffs2-nand"; }; partition@12000000 { reg = <0x12000000 0x10000000>; label = "ramdisk-nand"; read-only; }; partition@22000000 { reg = <0x22000000 0x04000000>; label = "kernel-nand"; }; partition@26000000 { reg = <0x26000000 0x01000000>; label = "dtb-nand"; read-only; }; partition@27000000 { reg = <0x27000000 0x19000000>; label = "reserved-nand"; }; }; }; soc@ffe00000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,p1022-immr", "simple-bus"; ranges = <0x0 0 0xffe00000 0x100000>; bus-frequency = <0>; // Filled out by uboot. ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <12>; }; ecm@1000 { compatible = "fsl,p1022-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <16 2>; interrupt-parent = <&mpic>; }; memory-controller@2000 { compatible = "fsl,p1022-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <16 2>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; ssi@15000 { compatible = "fsl,p1022-ssi"; cell-index = <0>; reg = <0x15000 0x100>; interrupt-parent = <&mpic>; interrupts = <75 2>; fsl,mode = "i2s-slave"; codec-handle = <&wm8960>; fsl,playback-dma = <&dma00>; fsl,capture-dma = <&dma01>; fsl,fifo-depth = <15>; fsl,ssi-asynchronous = <1>; }; i2c@3100 { #address-cells = <1>; #size-cells = <0>; cell-index = <1>; compatible = "fsl-i2c"; reg = <0x3100 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; rtc@68{ compatible = "dallas,ds3232"; reg = <0x68>; interrupts = <16 0x2>; interrupt-parent = <&mpic>; }; adt7461@4c{ compatible = "adi,adt7461"; reg = <0x4c>; }; zl6100@21{ compatible = "intersil,zl6100"; reg = <0x21>; }; zl6100@24{ compatible = "intersil,zl6100"; reg = <0x24>; }; zl6100@26{ compatible = "intersil,zl6100"; reg = <0x26>; }; zl6100@29{ compatible = "intersil,zl6100"; reg = <0x29>; }; wm8960:codec@1a { compatible = "wolfson,wm8960"; reg = <0x1a>; clock-frequency = <0xbb8000>; }; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "ns16550"; reg = <0x4500 0x100>; clock-frequency = <0>; //interrupts = <42 2>; Farrukh - Removing this will let kernel poll this. Since the interrupt is shared so it can cause problem to userspace programs. //interrupt-parent = <&mpic>; }; //serial1: serial@4600 { // cell-index = <1>; // device_type = "serial"; // compatible = "ns16550"; // reg = <0x4600 0x100>; // clock-frequency = <0>; // interrupts = <42 2>; // interrupt-parent = <&mpic>; //}; spi@7000 { cell-index = <0>; #address-cells = <1>; #size-cells = <0>; compatible = "fsl,espi"; reg = <0x7000 0x1000>; interrupts = <59 0x2>; interrupt-parent = <&mpic>; espi,num-ss-bits = <4>; mode = "cpu"; fsl_m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,espi-flash"; reg = <0>; linux,modalias = "fsl_m25p80"; spi-max-frequency = <40000000>; /* input clock */ partition@0 { label = "u-boot-spi"; reg = <0x00000000 0x00100000>; read-only; }; partition@100000 { label = "kernel-spi"; reg = <0x00100000 0x00500000>; read-only; }; partition@600000 { label = "dtb-spi"; reg = <0x00600000 0x00100000>; read-only; }; partition@700000 { label = "file system-spi"; reg = <0x00700000 0x00900000>; }; }; }; dma@c300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,eloplus-dma"; reg = <0xc300 0x4>; ranges = <0x0 0xc100 0x200>; cell-index = <1>; dma-channel@0 { compatible = "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <76 2>; }; dma-channel@80 { compatible = "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <77 2>; }; dma-channel@100 { compatible = "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <78 2>; }; dma-channel@180 { compatible = "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <79 2>; }; }; gpio: gpio-controller@f000 { #gpio-cells = <2>; compatible = "fsl,mpc8572-gpio"; reg = <0xf000 0x100>; interrupts = <47 0x2>; interrupt-parent = <&mpic>; gpio-controller; }; L2: l2-cache-controller@20000 { compatible = "fsl,p1022-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; //interrupts = <16 2>; }; dma@21300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,eloplus-dma"; reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; dma00: dma-channel@0 { compatible = "fsl,ssi-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <20 2>; }; dma01: dma-channel@80 { compatible = "fsl,ssi-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <23 2>; }; }; usb@22000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-usb2-dr"; reg = <0x22000 0x1000>; interrupt-parent = <&mpic>; interrupts = <28 0x2>; phy_type = "ulpi"; }; usb@23000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-usb2-dr"; reg = <0x23000 0x1000>; interrupt-parent = <&mpic>; interrupts = <46 0x2>; phy_type = "ulpi"; }; mdio@24000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,etsec2-mdio"; reg = <0x24000 0x1000 0xb0030 0x4>; // phy0: ethernet-phy@0 { // interrupt-parent = <&mpic>; // interrupts = <3 1>; // reg = <0x1>; // }; // phy1: ethernet-phy@1 { // interrupt-parent = <&mpic>; // interrupts = <9 1>; // reg = <0x2>; // }; }; //mdio@25000 { // #address-cells = <1>; // #size-cells = <0>; // compatible = "fsl,etsec2-mdio"; // reg = <0x25000 0x1000 0xb1030 0x4>; //}; //enet0: ethernet@B0000 { // #address-cells = <1>; // #size-cells = <1>; // cell-index = <0>; // device_type = "network"; // model = "eTSEC"; // compatible = "fsl,etsec2"; // fsl,num_rx_queues = <0x8>; // fsl,num_tx_queues = <0x8>; // fsl,magic-packet; // fsl,wake-on-filer; // clk-handle = <&etsec1_clk>; // local-mac-address = [ 00 00 00 00 00 00 ]; // interrupt-parent = <&mpic>; // //fixed-link = <1 1 1000 0 0>; // phy-handle = <&phy0>; // phy-connection-type = "rgmii-id"; // queue-group@0{ // #address-cells = <1>; // #size-cells = <1>; // reg = <0xB0000 0x1000>; // interrupts = <29 2 30 2 34 2>; // }; // queue-group@1{ // #address-cells = <1>; // #size-cells = <1>; // reg = <0xB4000 0x1000>; // interrupts = <17 2 18 2 24 2>; // }; //}; enet1: ethernet@B1000 { #address-cells = <1>; #size-cells = <1>; cell-index = <0>; device_type = "network"; model = "eTSEC"; compatible = "fsl,etsec2"; fsl,num_rx_queues = <0x8>; fsl,num_tx_queues = <0x8>; clk-handle = <&etsec2_clk>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupt-parent = <&mpic>; //fixed-link = <1 1 1000 0 0>; fixed-link = <1 1 100 0 0>; //phy-handle = <&phy1>; phy-connection-type = "rgmii-id"; queue-group@0{ #address-cells = <1>; #size-cells = <1>; reg = <0xB1000 0x1000>; interrupts = <35 2 36 2 40 2>; }; queue-group@1{ #address-cells = <1>; #size-cells = <1>; reg = <0xB5000 0x1000>; interrupts = <51 2 52 2 67 2>; }; }; sdhci@2e000 { compatible = "fsl,p1022-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <72 0x2>; interrupt-parent = <&mpic>; fsl,sdhci-auto-cmd12; /* Filled in by U-Boot */ clock-frequency = <0>; }; crypto@30000 { compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <45 2 58 2>; interrupt-parent = <&mpic>; fsl,num-channels = <4>; fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0x97c>; fsl,descriptor-types-mask = <0x3a30abf>; // fsl,multi-host-mode = "dual"; fsl,channel-remap = <0x3>; }; sata@18000 { compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; reg = <0x18000 0x1000>; cell-index = <1>; interrupts = <74 0x2>; interrupt-parent = <&mpic>; }; sata@19000 { compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; reg = <0x19000 0x1000>; cell-index = <2>; interrupts = <41 0x2>; interrupt-parent = <&mpic>; }; display@10000 { compatible = "fsl,diu", "fsl,p1022-diu"; reg = <0x10000 1000>; interrupts = <64 2>; interrupt-parent = <&mpic>; }; power@e0070{ compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc", "fsl,p1022-pmc"; reg = <0xe0070 0x20>; etsec1_clk: soc-clk@B0{ fsl,pmcdr-mask = <0x00000080>; }; etsec2_clk: soc-clk@B1{ fsl,pmcdr-mask = <0x00000040>; }; }; timer@41100 { compatible = "fsl,mpic-global-timer"; reg = <0x41100 0x204>; interrupts = <0xf7 0x2>; interrupt-parent = <&mpic>; }; mpic: pic@40000 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; //compatible = "fsl,mpic"; device_type = "open-pic"; pic-no-reset; protected-sources = < 16 // l2-cache-controller@20000 3 // ethernet-phy@0 29 30 34 // queue-group@0 17 18 24 // gueue-group@1 42 // serial@4500 >; }; //message@41400 { // compatible = "fsl,p1022-msg","fsl,mpic-msg"; // reg = <0x41400 0x200>; // cell-index = <1>; // interrupts = <0xb0 2 0xb1 2 0xb2 2 0xb3 2>; // interrupt-parent = < &mpic >; //}; //message@42400 { // compatible = "fsl,p1022-msg","fsl,mpic-msg"; // reg = <0x42400 0x200>; // cell-index = <2>; // interrupts = <0xb4 2 0xb5 2 0xb6 2 0xb7 2>; // interrupt-parent = < &mpic >; //}; msi@41600 { compatible = "fsl,mpic-msi"; reg = <0x41600 0x80>; msi-available-ranges = <0 0x100>; interrupts = < 0xe0 0 0xe1 0 0xe2 0 0xe3 0 0xe4 0 0xe5 0 0xe6 0 0xe7 0>; interrupt-parent = <&mpic>; }; global-utilities@e0000 { //global utilities block compatible = "fsl,p1022-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; }; pci0: pcie@ffe09000 { cell-index = <2>; compatible = "fsl,p1022-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0 0xffe09000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <16 2>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0 0 1 &mpic 4 1 0000 0 0 2 &mpic 5 1 0000 0 0 3 &mpic 6 1 0000 0 0 4 &mpic 7 1 >; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x100000>; }; }; pci1: pcie@ffe0a000 { cell-index = <1>; compatible = "fsl,p1022-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0 0xffe0a000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <16 2>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0 0 1 &mpic 0 1 0000 0 0 2 &mpic 1 1 0000 0 0 3 &mpic 2 1 0000 0 0 4 &mpic 3 1 >; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x2000000 0x0 0xc0000000 0x2000000 0x0 0xc0000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x100000>; }; }; pci2: pcie@ffe0b000 { cell-index = <3>; compatible = "fsl,p1022-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0 0xffe0b000 0 0x1000>; bus-range = <0 255>; ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <16 2>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0 0 1 &mpic 8 1 0000 0 0 2 &mpic 9 1 0000 0 0 3 &mpic 10 1 0000 0 0 4 &mpic 11 1 >; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x2000000 0x0 0x80000000 0x2000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x100000>; }; }; }; [-- Attachment #3: p1022rdk-core0.dts --] [-- Type: application/octet-stream, Size: 15749 bytes --] /* * P1022 RDK - Core 0 Device Tree Source * */ /dts-v1/; / { model = "fsl,P1022"; compatible = "fsl,P1022DS"; #address-cells = <2>; #size-cells = <2>; aliases { ethernet0 = &enet0; serial0 = &serial1; msgr-block0 = &msgr_block0; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,P1022@0 { device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; }; }; memory { device_type = "memory"; }; mcomm { compatible = "ment,mcomm"; //reg = <0 0x70000000 0 0x10000000>; //reg = <0 0x18000000 0 0x080000000>; reg = <0 0x18000000 0 0x008000000>; notifications = < 1 1 // Core 1, Msg Reg 1 0 0 // Core 0, Msg Reg 0 >; }; //localbus@ffe05000 { // #address-cells = <2>; // #size-cells = <1>; // compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; // reg = <0 0xffe05000 0 0x1000>; // interrupts = <19 2>; // interrupt-parent = <&mpic>; // ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 // 0x1 0x0 0x0 0xe0000000 0x08000000 // 0x2 0x0 0x0 0xffa00000 0x00040000 // 0x3 0x0 0x0 0xffdf0000 0x00008000>; // nor@0,0 { // #address-cells = <1>; // #size-cells = <1>; // compatible = "cfi-flash"; // reg = <0x0 0x0 0x8000000>; // bank-width = <2>; // device-width = <1>; // partition@0 { // reg = <0x0 0x03000000>; // label = "ramdisk-nor"; // read-only; // }; // partition@3000000 { // reg = <0x03000000 0x00e00000>; // label = "diagnostic-nor"; // read-only; // }; // partition@3e00000 { // reg = <0x03e00000 0x00200000>; // label = "dink-nor"; // read-only; // }; // partition@4000000 { // reg = <0x04000000 0x00400000>; // label = "kernel-nor"; // read-only; // }; // partition@4400000 { // reg = <0x04400000 0x03b00000>; // label = "jffs2-nor"; // }; // partition@7f00000 { // reg = <0x07f00000 0x00080000>; // label = "dtb-nor"; // read-only; // }; // partition@7f80000 { // reg = <0x07f80000 0x00080000>; // label = "u-boot-nor"; // read-only; // }; // }; // nand@2,0 { // #address-cells = <1>; // #size-cells = <1>; // compatible = "fsl,elbc-fcm-nand"; // reg = <0x2 0x0 0x40000>; // partition@0 { // reg = <0x0 0x02000000>; // label = "u-boot-nand"; // read-only; // }; // partition@2000000 { // reg = <0x02000000 0x10000000>; // label = "jffs2-nand"; // }; // partition@12000000 { // reg = <0x12000000 0x10000000>; // label = "ramdisk-nand"; // read-only; // }; // partition@22000000 { // reg = <0x22000000 0x04000000>; // label = "kernel-nand"; // }; // partition@26000000 { // reg = <0x26000000 0x01000000>; // label = "dtb-nand"; // read-only; // }; // partition@27000000 { // reg = <0x27000000 0x19000000>; // label = "reserved-nand"; // }; // }; //}; soc@ffe00000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,p1022-immr", "simple-bus"; ranges = <0x0 0 0xffe00000 0x100000>; bus-frequency = <0>; // Filled out by uboot. //ecm-law@0 { // compatible = "fsl,ecm-law"; // reg = <0x0 0x1000>; // fsl,num-laws = <12>; //}; //ecm@1000 { // compatible = "fsl,p1022-ecm", "fsl,ecm"; // reg = <0x1000 0x1000>; // interrupts = <16 2>; // interrupt-parent = <&mpic>; //}; //memory-controller@2000 { // compatible = "fsl,p1022-memory-controller"; // reg = <0x2000 0x1000>; // interrupt-parent = <&mpic>; // interrupts = <16 2>; //}; //i2c@3000 { // #address-cells = <1>; // #size-cells = <0>; // cell-index = <0>; // compatible = "fsl-i2c"; // reg = <0x3000 0x100>; // interrupts = <43 2>; // interrupt-parent = <&mpic>; // dfsrr; //}; //ssi@15000 { // compatible = "fsl,p1022-ssi"; // cell-index = <0>; // reg = <0x15000 0x100>; // interrupt-parent = <&mpic>; // interrupts = <75 2>; // fsl,mode = "i2s-slave"; // codec-handle = <&wm8776>; // fsl,playback-dma = <&dma00>; // fsl,capture-dma = <&dma01>; // fsl,fifo-depth = <15>; // fsl,ssi-asynchronous = <1>; //}; //i2c@3100 { // #address-cells = <1>; // #size-cells = <0>; // cell-index = <1>; // compatible = "fsl-i2c"; // reg = <0x3100 0x100>; // interrupts = <43 2>; // interrupt-parent = <&mpic>; // dfsrr; // rtc@68{ // compatible = "dallas,ds3232"; // reg = <0x68>; // interrupts = <16 0x2>; // interrupt-parent = <&mpic>; // }; // adt7461@4c{ // compatible = "adi,adt7461"; // reg = <0x4c>; // }; // zl6100@21{ // compatible = "intersil,zl6100"; // reg = <0x21>; // }; // zl6100@24{ // compatible = "intersil,zl6100"; // reg = <0x24>; // }; // zl6100@26{ // compatible = "intersil,zl6100"; // reg = <0x26>; // }; // zl6100@29{ // compatible = "intersil,zl6100"; // reg = <0x29>; // }; // wm8776:codec@1a { // compatible = "wolfson,wm8776"; // reg = <0x1a>; // clock-frequency = <0xbb8000>; // }; //}; //serial0: serial@4500 { // cell-index = <0>; // device_type = "serial"; // compatible = "ns16550"; // reg = <0x4500 0x100>; // clock-frequency = <0>; // interrupts = <42 2>; // interrupt-parent = <&mpic>; //}; serial1: serial@4600 { cell-index = <1>; device-type = "serial"; compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; // //interrupts = <42 2>; Farrukh - Removing this will let kernel poll this. Since the interrupt is shared so it can cause problem to userspace programs. // //interrupt-parent = <&mpic>; }; //spi@7000 { // cell-index = <0>; // #address-cells = <1>; // #size-cells = <0>; // compatible = "fsl,espi"; // reg = <0x7000 0x1000>; // interrupts = <59 0x2>; // interrupt-parent = <&mpic>; // espi,num-ss-bits = <4>; // mode = "cpu"; // fsl_m25p80@0 { // #address-cells = <1>; // #size-cells = <1>; // compatible = "fsl,espi-flash"; // reg = <0>; // linux,modalias = "fsl_m25p80"; // spi-max-frequency = <40000000>; /* input clock */ // partition@0 { // label = "u-boot-spi"; // reg = <0x00000000 0x00100000>; // read-only; // }; // partition@100000 { // label = "kernel-spi"; // reg = <0x00100000 0x00500000>; // read-only; // }; // partition@600000 { // label = "dtb-spi"; // reg = <0x00600000 0x00100000>; // read-only; // }; // partition@700000 { // label = "file system-spi"; // reg = <0x00700000 0x00900000>; // }; // }; //}; //gpio: gpio-controller@f000 { // #gpio-cells = <2>; // compatible = "fsl,mpc8572-gpio"; // reg = <0xf000 0x100>; // interrupts = <47 0x2>; // interrupt-parent = <&mpic>; // gpio-controller; //}; L2: l2-cache-controller@20000 { compatible = "fsl,p1022-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; interrupts = <16 2>; }; //dma@21300 { // #address-cells = <1>; // #size-cells = <1>; // compatible = "fsl,eloplus-dma"; // reg = <0x21300 0x4>; // ranges = <0x0 0x21100 0x200>; // cell-index = <0>; // dma00: dma-channel@0 { // compatible = "fsl,ssi-dma-channel"; // reg = <0x0 0x80>; // cell-index = <0>; // interrupt-parent = <&mpic>; // interrupts = <20 2>; // }; // dma01: dma-channel@80 { // compatible = "fsl,ssi-dma-channel"; // reg = <0x80 0x80>; // cell-index = <1>; // interrupt-parent = <&mpic>; // interrupts = <21 2>; // }; // dma-channel@100 { // compatible = "fsl,eloplus-dma-channel"; // reg = <0x100 0x80>; // cell-index = <2>; // interrupt-parent = <&mpic>; // interrupts = <22 2>; // }; // dma-channel@180 { // compatible = "fsl,eloplus-dma-channel"; // reg = <0x180 0x80>; // cell-index = <3>; // interrupt-parent = <&mpic>; // interrupts = <23 2>; // }; //}; //usb@22000 { // #address-cells = <1>; // #size-cells = <0>; // compatible = "fsl-usb2-dr"; // reg = <0x22000 0x1000>; // interrupt-parent = <&mpic>; // interrupts = <28 0x2>; // phy_type = "ulpi"; //}; mdio@24000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,etsec2-mdio"; reg = <0x24000 0x1000 0xb0030 0x4>; phy0: ethernet-phy@0 { interrupts = <3 1>; reg = <0x1>; }; phy1: ethernet-phy@1 { interrupts = <9 1>; reg = <0x2>; }; }; mdio@25000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,etsec2-mdio"; reg = <0x25000 0x1000 0xb1030 0x4>; }; enet0: ethernet@B0000 { #address-cells = <1>; #size-cells = <1>; cell-index = <0>; device_type = "network"; model = "eTSEC"; compatible = "fsl,etsec2"; fsl,num_rx_queues = <0x8>; fsl,num_tx_queues = <0x8>; fsl,magic-packet; fsl,wake-on-filer; clk-handle = <&etsec1_clk>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupt-parent = <&mpic>; phy-handle = <&phy0>; phy-connection-type = "rgmii-id"; queue-group@0{ #address-cells = <1>; #size-cells = <1>; reg = <0xB0000 0x1000>; interrupts = <29 2 30 2 34 2>; }; queue-group@1{ #address-cells = <1>; #size-cells = <1>; reg = <0xB4000 0x1000>; interrupts = <17 2 18 2 24 2>; }; }; //sdhci@2e000 { // compatible = "fsl,p1022-esdhc", "fsl,esdhc"; // reg = <0x2e000 0x1000>; // interrupts = <72 0x2>; // interrupt-parent = <&mpic>; // fsl,sdhci-auto-cmd12; // /* Filled in by U-Boot */ // clock-frequency = <0>; //}; //crypto@30000 { // compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", // "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; // reg = <0x30000 0x10000>; // interrupts = <45 2 58 2>; // interrupt-parent = <&mpic>; // fsl,num-channels = <4>; // fsl,channel-fifo-len = <24>; // fsl,exec-units-mask = <0xbfe>; // fsl,descriptor-types-mask = <0x3ab0ebf>; // fsl,multi-host-mode = "primary"; // fsl,channel-remap = <0x3>; //}; //sata@18000 { // compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; // reg = <0x18000 0x1000>; // cell-index = <1>; // interrupts = <74 0x2>; // interrupt-parent = <&mpic>; //}; //sata@19000 { // compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; // reg = <0x19000 0x1000>; // cell-index = <2>; // interrupts = <41 0x2>; // interrupt-parent = <&mpic>; //}; //display@10000 { // compatible = "fsl,diu", "fsl,p1022-diu"; // reg = <0x10000 1000>; // interrupts = <64 2>; // interrupt-parent = <&mpic>; //}; power@e0070{ compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc", "fsl,p1022-pmc"; reg = <0xe0070 0x20>; etsec1_clk: soc-clk@B0{ fsl,pmcdr-mask = <0x00000080>; }; etsec2_clk: soc-clk@B1{ fsl,pmcdr-mask = <0x00000040>; }; }; //timer@41100 { // compatible = "fsl,mpic-global-timer"; // reg = <0x41100 0x204>; // interrupts = <0xf7 0x2>; // interrupt-parent = <&mpic>; //}; mpic: pic@40000 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; pic-no-reset; protected-sources = < 19 // localbus@ffe0500 42 // serial@4600 72 // sdhci@2e000 16 // ecm@1000 // memory-controller@20000 // rtc@68 43 // i2c@3000, i2c@3100 75 // ssi@15000 59 // spi@7000 47 // gpio@f000 20 // dma-channel@0 21 // dma-channel@80 22 // dma-channel@100 23 // dma-channel@180 28 // usb@22000 9 // ethernet-phy@1 35 36 40 // queue-group@0 51 52 67 // queue-group@1 58 // crypto@30000 41 // sata@19000 74 // sata@18000 64 // display@10000 0xF7 // timer@41100 0xb1 // message@41400 16 // pci@ffe09000 // pci@ffe0a000 // pci@ffe0b000 0xe0 0xe1 0xe2 0xe3 // msi@41600 >; }; msgr_block0: message@41400 { compatible = "fsl,p1022-msg","fsl,mpic-msg", "fsl,mpic-v3.1-msgr"; reg = <0x41400 0x200>; cell-index = <1>; interrupts = <0xb0 2 0xb2 2 0xb3 2>; msg-receive-mask = <0xd>; interrupt-parent = < &mpic >; }; //msgr_block0: message@41400 { // compatible = "fsl,p1022-msg","fsl,mpic-msg", // "fsl,mpic-v3.1-msgr"; // reg = <0x41400 0x200>; // interrupts = <0xb0 0x2 0xb1 0x2 0xb2 0x2 0xb3 2>; // interrupt-parent = < &mpic >; //}; //msi@41600 { // compatible = "fsl,mpic-msi"; // reg = <0x41600 0x80>; // msi-available-ranges = <0 0x100>; // interrupts = < // 0xe0 0 // 0xe1 0 // 0xe2 0 // 0xe3 0 // 0xe4 0 // 0xe5 0 // 0xe6 0 // 0xe7 0>; // interrupt-parent = <&mpic>; //}; //global-utilities@e0000 { //global utilities block // compatible = "fsl,p1022-guts"; // reg = <0xe0000 0x1000>; // fsl,has-rstcr; //}; }; //pci0: pcie@ffe09000 { // cell-index = <2>; // compatible = "fsl,p1022-pcie"; // device_type = "pci"; // #interrupt-cells = <1>; // #size-cells = <2>; // #address-cells = <3>; // reg = <0 0xffe09000 0 0x1000>; // bus-range = <0 255>; // ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 // 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; // clock-frequency = <33333333>; // interrupt-parent = <&mpic>; // interrupts = <16 2>; // interrupt-map-mask = <0xf800 0 0 7>; // interrupt-map = < // /* IDSEL 0x0 */ // 0000 0 0 1 &mpic 4 1 // 0000 0 0 2 &mpic 5 1 // 0000 0 0 3 &mpic 6 1 // 0000 0 0 4 &mpic 7 1 // >; // pcie@0 { // reg = <0x0 0x0 0x0 0x0 0x0>; // #size-cells = <2>; // #address-cells = <3>; // device_type = "pci"; // ranges = <0x2000000 0x0 0xa0000000 // 0x2000000 0x0 0xa0000000 // 0x0 0x20000000 // 0x1000000 0x0 0x0 // 0x1000000 0x0 0x0 // 0x0 0x100000>; // }; //}; //pci1: pcie@ffe0a000 { // cell-index = <1>; // compatible = "fsl,p1022-pcie"; // device_type = "pci"; // #interrupt-cells = <1>; // #size-cells = <2>; // #address-cells = <3>; // reg = <0 0xffe0a000 0 0x1000>; // bus-range = <0 255>; // ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 // 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; // clock-frequency = <33333333>; // interrupt-parent = <&mpic>; // interrupts = <16 2>; // interrupt-map-mask = <0xf800 0 0 7>; // interrupt-map = < // /* IDSEL 0x0 */ // 0000 0 0 1 &mpic 0 1 // 0000 0 0 2 &mpic 1 1 // 0000 0 0 3 &mpic 2 1 // 0000 0 0 4 &mpic 3 1 // >; // pcie@0 { // reg = <0x0 0x0 0x0 0x0 0x0>; // #size-cells = <2>; // #address-cells = <3>; // device_type = "pci"; // ranges = <0x2000000 0x0 0xc0000000 // 0x2000000 0x0 0xc0000000 // 0x0 0x20000000 // 0x1000000 0x0 0x0 // 0x1000000 0x0 0x0 // 0x0 0x100000>; // }; //}; //pci2: pcie@ffe0b000 { // cell-index = <3>; // compatible = "fsl,p1022-pcie"; // device_type = "pci"; // #interrupt-cells = <1>; // #size-cells = <2>; // #address-cells = <3>; // reg = <0 0xffe0b000 0 0x1000>; // bus-range = <0 255>; // ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 // 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; // clock-frequency = <33333333>; // interrupt-parent = <&mpic>; // interrupts = <16 2>; // interrupt-map-mask = <0xf800 0 0 7>; // interrupt-map = < // /* IDSEL 0x0 */ // 0000 0 0 1 &mpic 8 1 // 0000 0 0 2 &mpic 9 1 // 0000 0 0 3 &mpic 10 1 // 0000 0 0 4 &mpic 11 1 // >; // pcie@0 { // reg = <0x0 0x0 0x0 0x0 0x0>; // #size-cells = <2>; // #address-cells = <3>; // device_type = "pci"; // ranges = <0x2000000 0x0 0x80000000 // 0x2000000 0x0 0x80000000 // 0x0 0x20000000 // 0x1000000 0x0 0x0 // 0x1000000 0x0 0x0 // 0x0 0x100000>; // }; //}; }; ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2011-12-08 15:24 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-12-07 14:57 Multi-OS on P1022RDK Failing Arshad, Farrukh 2011-12-07 21:24 ` Scott Wood 2011-12-08 6:35 ` Arshad, Farrukh 2011-12-08 15:24 ` Arshad, Farrukh
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