* [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
@ 2011-12-06 8:54 Shengzhou Liu
2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu
2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood
0 siblings, 2 replies; 11+ messages in thread
From: Shengzhou Liu @ 2011-12-06 8:54 UTC (permalink / raw)
To: linuxppc-dev; +Cc: scottwood, dwmw2, kumar.gala, linux-mtd, Shengzhou Liu
There was a bug for fmr initialization, which lead to fmr was always 0x100
in fsl_elbc_chip_init() and caused FCM command timeout before calling
fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum timeout value
and not relying on the setting of bootloader.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
v2: make fmr not relying on the setting of bootloader.
drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index eedd8ee..4f405a0 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
if (chip->pagemask & 0xff000000)
al++;
- /* add to ECCM mode set in fsl_elbc_init */
- priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
- (al << FMR_AL_SHIFT);
+ priv->fmr |= al << FMR_AL_SHIFT;
dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
chip->numchips);
@@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
priv->mtd.priv = chip;
priv->mtd.owner = THIS_MODULE;
- /* Set the ECCM according to the settings in bootloader.*/
- priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
+ /* set timeout to maximum */
+ priv->fmr = 15 << FMR_CWTO_SHIFT;
+ if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
+ priv->fmr |= FMR_ECCM;
/* fill in nand_chip structure */
/* set up function call table */
--
1.6.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
2011-12-06 8:54 [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller Shengzhou Liu
@ 2011-12-06 8:54 ` Shengzhou Liu
2011-12-06 17:17 ` Scott Wood
2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood
1 sibling, 1 reply; 11+ messages in thread
From: Shengzhou Liu @ 2011-12-06 8:54 UTC (permalink / raw)
To: linuxppc-dev; +Cc: scottwood, dwmw2, kumar.gala, linux-mtd, Shengzhou Liu
- fix NAND_CMD_READID command for ONFI detect.
- add NAND_CMD_PARAM command to read the ONFI parameter page.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
v2: no changes
drivers/mtd/nand/fsl_elbc_nand.c | 19 ++++++++++++-------
1 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 4f405a0..b4db407 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -349,19 +349,24 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
fsl_elbc_run_command(mtd);
return;
- /* READID must read all 5 possible bytes while CEB is active */
case NAND_CMD_READID:
- dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
+ case NAND_CMD_PARAM:
+ dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
(FIR_OP_UA << FIR_OP1_SHIFT) |
(FIR_OP_RBW << FIR_OP2_SHIFT));
- out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
- /* nand_get_flash_type() reads 8 bytes of entire ID string */
- out_be32(&lbc->fbcr, 8);
- elbc_fcm_ctrl->read_bytes = 8;
+ out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
+ /* reads 8 bytes of entire ID string */
+ if (NAND_CMD_READID == command) {
+ out_be32(&lbc->fbcr, 8);
+ elbc_fcm_ctrl->read_bytes = 8;
+ } else {
+ out_be32(&lbc->fbcr, 256);
+ elbc_fcm_ctrl->read_bytes = 256;
+ }
elbc_fcm_ctrl->use_mdr = 1;
- elbc_fcm_ctrl->mdr = 0;
+ elbc_fcm_ctrl->mdr = column;
set_addr(mtd, 0, 0, 0);
fsl_elbc_run_command(mtd);
--
1.6.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
2011-12-06 8:54 [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller Shengzhou Liu
2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu
@ 2011-12-06 17:16 ` Scott Wood
2011-12-07 6:30 ` Liu Shengzhou-B36685
1 sibling, 1 reply; 11+ messages in thread
From: Scott Wood @ 2011-12-06 17:16 UTC (permalink / raw)
To: Shengzhou Liu; +Cc: linux-mtd, kumar.gala, linuxppc-dev, dwmw2
On 12/06/2011 02:54 AM, Shengzhou Liu wrote:
> There was a bug for fmr initialization, which lead to fmr was always 0x100
> in fsl_elbc_chip_init() and caused FCM command timeout before calling
> fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum timeout value
> and not relying on the setting of bootloader.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
> v2: make fmr not relying on the setting of bootloader.
>
> drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++-----
> 1 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
> index eedd8ee..4f405a0 100644
> --- a/drivers/mtd/nand/fsl_elbc_nand.c
> +++ b/drivers/mtd/nand/fsl_elbc_nand.c
> @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
> if (chip->pagemask & 0xff000000)
> al++;
>
> - /* add to ECCM mode set in fsl_elbc_init */
> - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
> - (al << FMR_AL_SHIFT);
> + priv->fmr |= al << FMR_AL_SHIFT;
>
> dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
> chip->numchips);
> @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
> priv->mtd.priv = chip;
> priv->mtd.owner = THIS_MODULE;
>
> - /* Set the ECCM according to the settings in bootloader.*/
> - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
> + /* set timeout to maximum */
> + priv->fmr = 15 << FMR_CWTO_SHIFT;
> + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
> + priv->fmr |= FMR_ECCM;
Please do not change the way ECCM is handled. We probably should have
done it this way from the start, but at this point it breaks
compatibility if you have a large page flash and the firmware didn't
touch NAND.
-Scott
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu
@ 2011-12-06 17:17 ` Scott Wood
2011-12-07 3:16 ` Liu Shengzhou-B36685
0 siblings, 1 reply; 11+ messages in thread
From: Scott Wood @ 2011-12-06 17:17 UTC (permalink / raw)
To: Shengzhou Liu; +Cc: linux-mtd, kumar.gala, linuxppc-dev, dwmw2
On 12/06/2011 02:54 AM, Shengzhou Liu wrote:
> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
> index 4f405a0..b4db407 100644
> --- a/drivers/mtd/nand/fsl_elbc_nand.c
> +++ b/drivers/mtd/nand/fsl_elbc_nand.c
> @@ -349,19 +349,24 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
> fsl_elbc_run_command(mtd);
> return;
>
> - /* READID must read all 5 possible bytes while CEB is active */
> case NAND_CMD_READID:
> - dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
> + case NAND_CMD_PARAM:
> + dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
>
> out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
> (FIR_OP_UA << FIR_OP1_SHIFT) |
> (FIR_OP_RBW << FIR_OP2_SHIFT));
> - out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
> - /* nand_get_flash_type() reads 8 bytes of entire ID string */
> - out_be32(&lbc->fbcr, 8);
> - elbc_fcm_ctrl->read_bytes = 8;
> + out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
> + /* reads 8 bytes of entire ID string */
> + if (NAND_CMD_READID == command) {
if (command == NAND_CMD_READID) {
> + out_be32(&lbc->fbcr, 8);
> + elbc_fcm_ctrl->read_bytes = 8;
> + } else {
> + out_be32(&lbc->fbcr, 256);
> + elbc_fcm_ctrl->read_bytes = 256;
> + }
Any harm in always using 256?
-Scott
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
2011-12-06 17:17 ` Scott Wood
@ 2011-12-07 3:16 ` Liu Shengzhou-B36685
2011-12-07 17:16 ` Scott Wood
0 siblings, 1 reply; 11+ messages in thread
From: Liu Shengzhou-B36685 @ 2011-12-07 3:16 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood
@ 2011-12-07 6:30 ` Liu Shengzhou-B36685
2011-12-07 17:17 ` Scott Wood
0 siblings, 1 reply; 11+ messages in thread
From: Liu Shengzhou-B36685 @ 2011-12-07 6:30 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org
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dXJlIENXVE8gdGltZW91dCBpcyBzZXQgdG8gbWF4aW11bS4gIA0K
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
2011-12-07 3:16 ` Liu Shengzhou-B36685
@ 2011-12-07 17:16 ` Scott Wood
2011-12-08 3:06 ` Liu Shengzhou-B36685
0 siblings, 1 reply; 11+ messages in thread
From: Scott Wood @ 2011-12-07 17:16 UTC (permalink / raw)
To: Liu Shengzhou-B36685
Cc: Wood Scott-B07421, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org,
linux-mtd@lists.infradead.org
On 12/06/2011 09:16 PM, Liu Shengzhou-B36685 wrote:
>>> + out_be32(&lbc->fbcr, 8);
>>> + elbc_fcm_ctrl->read_bytes = 8;
>>> + } else {
>>> + out_be32(&lbc->fbcr, 256);
>>> + elbc_fcm_ctrl->read_bytes = 256;
>>> + }
>>
>> Any harm in always using 256?
>>
>> -Scott
> [Shengzhou] For NAND_CMD_READID command, the total bytes of entire ID string are 8, there are not 256 bytes so many, it's unnecessary and looks not so well logically to always using 256, though it works.
It's not performance critical, and always using 256 keeps things
simpler, and more robust if the length of the ID string grows in the
future (we used to assume it was 5 bytes...).
-Scott
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
2011-12-07 6:30 ` Liu Shengzhou-B36685
@ 2011-12-07 17:17 ` Scott Wood
2011-12-08 3:36 ` Liu Shengzhou-B36685
0 siblings, 1 reply; 11+ messages in thread
From: Scott Wood @ 2011-12-07 17:17 UTC (permalink / raw)
To: Liu Shengzhou-B36685
Cc: Wood Scott-B07421, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org,
linux-mtd@lists.infradead.org
On 12/07/2011 12:30 AM, Liu Shengzhou-B36685 wrote:
>
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Wednesday, December 07, 2011 1:16 AM
>> To: Liu Shengzhou-B36685
>> Cc: linuxppc-dev@lists.ozlabs.org; linux-mtd@lists.infradead.org;
>> dwmw2@infradead.org; Gala Kumar-B11780
>> Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of
>> Freescale NAND controller
>>
>> On 12/06/2011 02:54 AM, Shengzhou Liu wrote:
>>> There was a bug for fmr initialization, which lead to fmr was always
>>> 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before
>>> calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum
>>> timeout value and not relying on the setting of bootloader.
>>>
>>> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
>>> ---
>>> v2: make fmr not relying on the setting of bootloader.
>>>
>>> drivers/mtd/nand/fsl_elbc_nand.c | 10 +++++-----
>>> 1 files changed, 5 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c
>>> b/drivers/mtd/nand/fsl_elbc_nand.c
>>> index eedd8ee..4f405a0 100644
>>> --- a/drivers/mtd/nand/fsl_elbc_nand.c
>>> +++ b/drivers/mtd/nand/fsl_elbc_nand.c
>>> @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info
>> *mtd)
>>> if (chip->pagemask & 0xff000000)
>>> al++;
>>>
>>> - /* add to ECCM mode set in fsl_elbc_init */
>>> - priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
>>> - (al << FMR_AL_SHIFT);
>>> + priv->fmr |= al << FMR_AL_SHIFT;
>>>
>>> dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
>>> chip->numchips);
>>> @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd
>> *priv)
>>> priv->mtd.priv = chip;
>>> priv->mtd.owner = THIS_MODULE;
>>>
>>> - /* Set the ECCM according to the settings in bootloader.*/
>>> - priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
>>> + /* set timeout to maximum */
>>> + priv->fmr = 15 << FMR_CWTO_SHIFT;
>>> + if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
>>> + priv->fmr |= FMR_ECCM;
>>
>> Please do not change the way ECCM is handled. We probably should have
>> done it this way from the start, but at this point it breaks
>> compatibility if you have a large page flash and the firmware didn't
>> touch NAND.
>>
>> -Scott
> [Shengzhou] This patch doesn't change the way ECCM is handled, it's still same as before, just make sure CWTO timeout is set to maximum.
It does change it. It used to use the existing value in FMR, and now it
sets it based on ORn[PGS].
-Scott
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
2011-12-07 17:16 ` Scott Wood
@ 2011-12-08 3:06 ` Liu Shengzhou-B36685
0 siblings, 0 replies; 11+ messages in thread
From: Liu Shengzhou-B36685 @ 2011-12-08 3:06 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
2011-12-07 17:17 ` Scott Wood
@ 2011-12-08 3:36 ` Liu Shengzhou-B36685
2011-12-08 18:00 ` Scott Wood
0 siblings, 1 reply; 11+ messages in thread
From: Liu Shengzhou-B36685 @ 2011-12-08 3:36 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: linux-mtd@lists.infradead.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
2011-12-08 3:36 ` Liu Shengzhou-B36685
@ 2011-12-08 18:00 ` Scott Wood
0 siblings, 0 replies; 11+ messages in thread
From: Scott Wood @ 2011-12-08 18:00 UTC (permalink / raw)
To: Liu Shengzhou-B36685
Cc: Wood Scott-B07421, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, dwmw2@infradead.org,
linux-mtd@lists.infradead.org
On 12/07/2011 09:36 PM, Liu Shengzhou-B36685 wrote:
>
>
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Thursday, December 08, 2011 1:17 AM
>> To: Liu Shengzhou-B36685
>> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux-
>> mtd@lists.infradead.org; dwmw2@infradead.org; Gala Kumar-B11780
>> Subject: Re: [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of
>> Freescale NAND controller
>>
>> On 12/07/2011 12:30 AM, Liu Shengzhou-B36685 wrote:
>>> [Shengzhou] This patch doesn't change the way ECCM is handled, it's
>> still same as before, just make sure CWTO timeout is set to maximum.
>>
>> It does change it. It used to use the existing value in FMR, and now it
>> sets it based on ORn[PGS].
>>
>> -Scott
>
> [Shengzhou]
> In u-boot:
> #ifdef CONFIG_FSL_ELBC_FMR
> priv->fmr = CONFIG_FSL_ELBC_FMR;
> #else
> priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
> or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
> if (or & OR_FCM_PGS)
> priv->fmr |= FMR_ECCM;
> #endif
>
> In kernel: It used to be " priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM
> ", so fmr was always 0x100(or 0,depend on ORn[PGS]), CWTO was
> 0(timeout was minimum). In this patch, for not relying on
> bootloader, fmr is initialized as what u-boot does, except
> FMR_AL_SHIFT is handled in fsl_elbc_chip_init_tail and without
> definition of CONFIG_FSL_ELBC_FMR.
>
> So, it doesn't change it.
You're assuming that the above U-Boot code is always run. This depends
on whether the NAND driver is enabled in U-Boot.
In the future, though, it might also depend on whether a NAND command is
actually run in U-Boot -- this makes the setting of FMR
non-deterministic between boots, which is worse than a one-time breakage
of an unusual setup (driver not enabled in U-Boot at all).
So it is a change, but I now think it's a change we should make. The
changelog should mention that this is happening, though.
> Do we still need CONFIG_FSL_ELBC_FMR in kernel?
We do not want such a compile-time constant in the kernel. Use ORn[PGS]
as the patch currently does.
-Scott
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2011-12-08 18:00 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-12-06 8:54 [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller Shengzhou Liu
2011-12-06 8:54 ` [PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL " Shengzhou Liu
2011-12-06 17:17 ` Scott Wood
2011-12-07 3:16 ` Liu Shengzhou-B36685
2011-12-07 17:16 ` Scott Wood
2011-12-08 3:06 ` Liu Shengzhou-B36685
2011-12-06 17:16 ` [PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale " Scott Wood
2011-12-07 6:30 ` Liu Shengzhou-B36685
2011-12-07 17:17 ` Scott Wood
2011-12-08 3:36 ` Liu Shengzhou-B36685
2011-12-08 18:00 ` Scott Wood
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