From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-ID: <4FDF7EBC.8090604@freescale.com> Date: Mon, 18 Jun 2012 14:17:16 -0500 From: Scott Wood MIME-Version: 1.0 To: Sethi Varun-B16395 Subject: Re: [PATCH 4/4] powerpc/mpic: FSL MPIC error interrupt support. References: <1332850633-23661-1-git-send-email-Varun.Sethi@freescale.com> <7F9EFF8D-82E4-414E-BB76-24BE84F2D8BC@kernel.crashing.org> <4F720FE3.7080101@freescale.com> <7376AC30-8A8F-4A3E-A025-C8F92AFE23E5@kernel.crashing.org> In-Reply-To: Content-Type: text/plain; charset="ISO-8859-1" Cc: Wood Scott-B07421 , "Linuxppc-dev@lists.ozlabs.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 06/18/2012 02:12 PM, Sethi Varun-B16395 wrote: > > >>>> +/* >>>>> + * Error interrupt registers >>>>> + */ >>>>> + >>>>> +#define MPIC_ERR_INT_BASE 0x3900 >>>>> +#define MPIC_ERR_INT_EISR 0x0000 >>>>> +#define MPIC_ERR_INT_EIMR 0x0010 >>>>> + >>>>> #define MPIC_MAX_IRQ_SOURCES 2048 >>>>> #define MPIC_MAX_CPUS 32 >>>>> #define MPIC_MAX_ISU 32 >>>>> >>>>> #define MPIC_MAX_TIMER 8 >>>>> #define MPIC_MAX_IPI 4 >>>>> +#define MPIC_MAX_ERR 32 >>>> >>>> Should probably be 64 >>> >>> This patch supports MPIC 4.1 and EISR0. When support is added for >>> EISR1 (didn't realize this was coming until your comment prompted me >>> to check...), this should be updated, but this change alone would not >>> make it work. >> >> Would prefer we handle this now rather than later (T4240 is going to need >> EISR1 support). > Hi Kumar, > As of now I don't have a proper mechanism to test this functionality. I will > submit a follow up patch for EISR1/EIMR1 support once I have a mechanism to > test this functionality. You could still write the code in a way that scales to multiple EISRs, and test that it works with EISR0. -Scott