From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from db3outboundpool.messaging.microsoft.com (db3ehsobe004.messaging.microsoft.com [213.199.154.142]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id AC9B4B6F9A for ; Sat, 30 Jun 2012 03:11:56 +1000 (EST) Message-ID: <4FEDE184.7070109@freescale.com> Date: Fri, 29 Jun 2012 12:10:28 -0500 From: Scott Wood MIME-Version: 1.0 To: Timur Tabi Subject: Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync References: <1340706359-9455-1-git-send-email-chenhui.zhao@freescale.com> <4FEDD07D.3090103@freescale.com> <4FEDD1F0.1060000@freescale.com> <4FEDD383.40804@freescale.com> <4FEDD3EB.7090606@freescale.com> In-Reply-To: <4FEDD3EB.7090606@freescale.com> Content-Type: text/plain; charset="UTF-8" Cc: Wood Scott-B07421 , Li Yang-R58472 , Zhao Chenhui-B35336 , "linux-kernel@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 06/29/2012 11:12 AM, Timur Tabi wrote: > Scott Wood wrote: >> Why is this different from anywhere else where we have a list of >> compatibles to match, often based on various SoCs? Note that we >> explicitly want to match only certain SoCs here. > > I was just hoping to find a way to avoid an ever increasing list of > compatible strings. PCI drivers have to put up with it, why should we be different? :-) > Other posts on this thread imply that this code could > work for all multi-core e500 parts. That list covers all multi-core e500v2 parts that I know of. Corenet based chips will need a slightly different implementation, since the registers are different. -Scott