* [PATCH 1/5] dt-bindings: arm64: add compatible for LX2160A
2018-08-20 6:47 [PATCH 0/5] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma
@ 2018-08-20 6:47 ` Vabhav Sharma
2018-08-20 6:47 ` [PATCH 2/5] soc/fsl/guts: Add compatible string " Vabhav Sharma
` (3 subsequent siblings)
4 siblings, 0 replies; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-20 6:47 UTC (permalink / raw)
To: linux-kernel, devicetree, robh+dt, mark.rutland, linuxppc-dev,
linux-arm-kernel, mturquette, sboyd, rjw, viresh.kumar, linux-clk,
linux-pm, linux-kernel-owner, catalin.marinas, will.deacon,
gregkh, arnd, kstewart, yamada.masahiro
Cc: linux, V.Sethi, udit.kumar, Vabhav Sharma
Add compatible for LX2160A SoC,QDS and RDB board
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index cdb9dd7..76256bd 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -218,3 +218,15 @@ Required root node properties:
LS2088A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
+
+LX2160A SoC
+Required root node properties:
+ - compatible = "fsl,lx2160a";
+
+LX2160A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
+
+LX2160A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 2/5] soc/fsl/guts: Add compatible string for LX2160A
2018-08-20 6:47 [PATCH 0/5] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma
2018-08-20 6:47 ` [PATCH 1/5] dt-bindings: arm64: add compatible for LX2160A Vabhav Sharma
@ 2018-08-20 6:47 ` Vabhav Sharma
2018-08-20 6:47 ` [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma
` (2 subsequent siblings)
4 siblings, 0 replies; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-20 6:47 UTC (permalink / raw)
To: linux-kernel, devicetree, robh+dt, mark.rutland, linuxppc-dev,
linux-arm-kernel, mturquette, sboyd, rjw, viresh.kumar, linux-clk,
linux-pm, linux-kernel-owner, catalin.marinas, will.deacon,
gregkh, arnd, kstewart, yamada.masahiro
Cc: linux, V.Sethi, udit.kumar, Vabhav Sharma
Adding compatible string "lx2160a-dcfg" to
initialize guts driver for lx2160
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
drivers/soc/fsl/guts.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 302e0c8..5e1e633 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -222,6 +222,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1088a-dcfg", },
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", },
+ { .compatible = "fsl,lx2160a-dcfg", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-20 6:47 [PATCH 0/5] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma
2018-08-20 6:47 ` [PATCH 1/5] dt-bindings: arm64: add compatible for LX2160A Vabhav Sharma
2018-08-20 6:47 ` [PATCH 2/5] soc/fsl/guts: Add compatible string " Vabhav Sharma
@ 2018-08-20 6:47 ` Vabhav Sharma
2018-08-28 22:39 ` Stephen Boyd
2018-08-29 0:18 ` Scott Wood
2018-08-20 6:47 ` [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support Vabhav Sharma
2018-08-20 6:47 ` [PATCH 5/5] arm64: dts: add LX2160ARDB board support Vabhav Sharma
4 siblings, 2 replies; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-20 6:47 UTC (permalink / raw)
To: linux-kernel, devicetree, robh+dt, mark.rutland, linuxppc-dev,
linux-arm-kernel, mturquette, sboyd, rjw, viresh.kumar, linux-clk,
linux-pm, linux-kernel-owner, catalin.marinas, will.deacon,
gregkh, arnd, kstewart, yamada.masahiro
Cc: linux, V.Sethi, udit.kumar, Yogesh Gaur, Tang Yuantian,
Vabhav Sharma
From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Add clockgen support for lx2160a.
Added entry for compat 'fsl,lx2160a-clockgen'.
As LX2160A is 16 core, so modified value for NUM_CMUX
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
drivers/clk/clk-qoriq.c | 14 +++++++++++++-
drivers/cpufreq/qoriq-cpufreq.c | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..fc6e308 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -60,7 +60,7 @@ struct clockgen_muxinfo {
};
#define NUM_HWACCEL 5
-#define NUM_CMUX 8
+#define NUM_CMUX 16
struct clockgen;
@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
},
{
+ .compat = "fsl,lx2160a-clockgen",
+ .cmux_groups = {
+ &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+ },
+ .cmux_to_group = {
+ 0, 0, 0, 0, 1, 1, 1, 1, -1
+ },
+ .pll_mask = 0x37,
+ .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+ },
+ {
.compat = "fsl,p2041-clockgen",
.guts_compat = "fsl,qoriq-device-config-1.0",
.init_periph = p2041_init_periph,
@@ -1424,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
/* Legacy nodes */
CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 3d773f6..83921b7 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -295,6 +295,7 @@ static const struct of_device_id node_matches[] __initconst = {
{ .compatible = "fsl,ls1046a-clockgen", },
{ .compatible = "fsl,ls1088a-clockgen", },
{ .compatible = "fsl,ls2080a-clockgen", },
+ { .compatible = "fsl,lx2160a-clockgen", },
{ .compatible = "fsl,p4080-clockgen", },
{ .compatible = "fsl,qoriq-clockgen-1.0", },
{ .compatible = "fsl,qoriq-clockgen-2.0", },
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-20 6:47 ` [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma
@ 2018-08-28 22:39 ` Stephen Boyd
2018-08-29 0:18 ` Scott Wood
1 sibling, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-08-28 22:39 UTC (permalink / raw)
To: Vabhav Sharma, arnd, catalin.marinas, devicetree, gregkh,
kstewart, linux-arm-kernel, linux-clk, linux-kernel-owner,
linux-kernel, linux-pm, linuxppc-dev, mark.rutland, mturquette,
rjw, robh+dt, viresh.kumar, will.deacon, yamada.masahiro
Cc: linux, V.Sethi, udit.kumar, Yogesh Gaur, Tang Yuantian,
Vabhav Sharma
Quoting Vabhav Sharma (2018-08-19 23:47:14)
> From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> =
> Add clockgen support for lx2160a.
> Added entry for compat 'fsl,lx2160a-clockgen'.
> As LX2160A is 16 core, so modified value for NUM_CMUX
> =
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-20 6:47 ` [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma
2018-08-28 22:39 ` Stephen Boyd
@ 2018-08-29 0:18 ` Scott Wood
2018-08-30 7:36 ` Vabhav Sharma
1 sibling, 1 reply; 23+ messages in thread
From: Scott Wood @ 2018-08-29 0:18 UTC (permalink / raw)
To: Vabhav Sharma, linux-kernel, devicetree, robh+dt, mark.rutland,
linuxppc-dev, linux-arm-kernel, mturquette, sboyd, rjw,
viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro
Cc: Yogesh Gaur, Tang Yuantian, udit.kumar, linux, V.Sethi
On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
>
> Add clockgen support for lx2160a.
> Added entry for compat 'fsl,lx2160a-clockgen'.
> As LX2160A is 16 core, so modified value for NUM_CMUX
>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
> drivers/clk/clk-qoriq.c | 14 +++++++++++++-
> drivers/cpufreq/qoriq-cpufreq.c | 1 +
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> index 3a1812f..fc6e308 100644
> --- a/drivers/clk/clk-qoriq.c
> +++ b/drivers/clk/clk-qoriq.c
> @@ -60,7 +60,7 @@ struct clockgen_muxinfo {
> };
>
> #define NUM_HWACCEL 5
> -#define NUM_CMUX 8
> +#define NUM_CMUX 16
>
> struct clockgen;
>
> @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
> .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> },
> {
> + .compat = "fsl,lx2160a-clockgen",
> + .cmux_groups = {
> + &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> + },
> + .cmux_to_group = {
> + 0, 0, 0, 0, 1, 1, 1, 1, -1
> + },
> + .pll_mask = 0x37,
> + .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> + },
Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8 entries in
cmux_to_group?
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-29 0:18 ` Scott Wood
@ 2018-08-30 7:36 ` Vabhav Sharma
2018-08-30 17:39 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-30 7:36 UTC (permalink / raw)
To: Scott Wood, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, Andy Tang, Udit Kumar, linux@armlinux.org.uk,
Varun Sethi
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogbGludXgta2VybmVsLW93
bmVyQHZnZXIua2VybmVsLm9yZyA8bGludXgta2VybmVsLQ0KPiBvd25lckB2Z2VyLmtlcm5lbC5v
cmc+IE9uIEJlaGFsZiBPZiBTY290dCBXb29kDQo+IFNlbnQ6IFdlZG5lc2RheSwgQXVndXN0IDI5
LCAyMDE4IDU6NDkgQU0NCj4gVG86IFZhYmhhdiBTaGFybWEgPHZhYmhhdi5zaGFybWFAbnhwLmNv
bT47IGxpbnV4LQ0KPiBrZXJuZWxAdmdlci5rZXJuZWwub3JnOyBkZXZpY2V0cmVlQHZnZXIua2Vy
bmVsLm9yZzsgcm9iaCtkdEBrZXJuZWwub3JnOw0KPiBtYXJrLnJ1dGxhbmRAYXJtLmNvbTsgbGlu
dXhwcGMtZGV2QGxpc3RzLm96bGFicy5vcmc7IGxpbnV4LWFybS0NCj4ga2VybmVsQGxpc3RzLmlu
ZnJhZGVhZC5vcmc7IG10dXJxdWV0dGVAYmF5bGlicmUuY29tOyBzYm95ZEBrZXJuZWwub3JnOw0K
PiByandAcmp3eXNvY2tpLm5ldDsgdmlyZXNoLmt1bWFyQGxpbmFyby5vcmc7IGxpbnV4LWNsa0B2
Z2VyLmtlcm5lbC5vcmc7DQo+IGxpbnV4LXBtQHZnZXIua2VybmVsLm9yZzsgbGludXgta2VybmVs
LW93bmVyQHZnZXIua2VybmVsLm9yZzsNCj4gY2F0YWxpbi5tYXJpbmFzQGFybS5jb207IHdpbGwu
ZGVhY29uQGFybS5jb207DQo+IGdyZWdraEBsaW51eGZvdW5kYXRpb24ub3JnOyBhcm5kQGFybmRi
LmRlOw0KPiBrc3Rld2FydEBsaW51eGZvdW5kYXRpb24ub3JnOyB5YW1hZGEubWFzYWhpcm9Ac29j
aW9uZXh0LmNvbQ0KPiBDYzogWW9nZXNoIE5hcmF5YW4gR2F1ciA8eW9nZXNobmFyYXlhbi5nYXVy
QG54cC5jb20+OyBBbmR5IFRhbmcNCj4gPGFuZHkudGFuZ0BueHAuY29tPjsgVWRpdCBLdW1hciA8
dWRpdC5rdW1hckBueHAuY29tPjsNCj4gbGludXhAYXJtbGludXgub3JnLnVrOyBWYXJ1biBTZXRo
aSA8Vi5TZXRoaUBueHAuY29tPg0KPiBTdWJqZWN0OiBSZTogW1BBVENIIDMvNV0gZHJpdmVyczog
Y2xrLXFvcmlxOiBBZGQgY2xvY2tnZW4gc3VwcG9ydCBmb3IgbHgyMTYwYQ0KPiANCj4gT24gTW9u
LCAyMDE4LTA4LTIwIGF0IDEyOjE3ICswNTMwLCBWYWJoYXYgU2hhcm1hIHdyb3RlOg0KPiA+IEZy
b206IFlvZ2VzaCBHYXVyIDx5b2dlc2huYXJheWFuLmdhdXJAbnhwLmNvbT4NCj4gPg0KPiA+IEFk
ZCBjbG9ja2dlbiBzdXBwb3J0IGZvciBseDIxNjBhLg0KPiA+IEFkZGVkIGVudHJ5IGZvciBjb21w
YXQgJ2ZzbCxseDIxNjBhLWNsb2NrZ2VuJy4NCj4gPiBBcyBMWDIxNjBBIGlzIDE2IGNvcmUsIHNv
IG1vZGlmaWVkIHZhbHVlIGZvciBOVU1fQ01VWA0KPiA+DQo+ID4gU2lnbmVkLW9mZi1ieTogVGFu
ZyBZdWFudGlhbiA8YW5keS50YW5nQG54cC5jb20+DQo+ID4gU2lnbmVkLW9mZi1ieTogWW9nZXNo
IEdhdXIgPHlvZ2VzaG5hcmF5YW4uZ2F1ckBueHAuY29tPg0KPiA+IFNpZ25lZC1vZmYtYnk6IFZh
YmhhdiBTaGFybWEgPHZhYmhhdi5zaGFybWFAbnhwLmNvbT4NCj4gPiAtLS0NCj4gPiAgZHJpdmVy
cy9jbGsvY2xrLXFvcmlxLmMgICAgICAgICB8IDE0ICsrKysrKysrKysrKystDQo+ID4gIGRyaXZl
cnMvY3B1ZnJlcS9xb3JpcS1jcHVmcmVxLmMgfCAgMSArDQo+ID4gIDIgZmlsZXMgY2hhbmdlZCwg
MTQgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQ0KPiA+DQo+ID4gZGlmZiAtLWdpdCBhL2Ry
aXZlcnMvY2xrL2Nsay1xb3JpcS5jIGIvZHJpdmVycy9jbGsvY2xrLXFvcmlxLmMgaW5kZXgNCj4g
PiAzYTE4MTJmLi5mYzZlMzA4IDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvY2xrL2Nsay1xb3Jp
cS5jDQo+ID4gKysrIGIvZHJpdmVycy9jbGsvY2xrLXFvcmlxLmMNCj4gPiBAQCAtNjAsNyArNjAs
NyBAQCBzdHJ1Y3QgY2xvY2tnZW5fbXV4aW5mbyB7ICB9Ow0KPiA+DQo+ID4gICNkZWZpbmUgTlVN
X0hXQUNDRUwJNQ0KPiA+IC0jZGVmaW5lIE5VTV9DTVVYCTgNCj4gPiArI2RlZmluZSBOVU1fQ01V
WAkxNg0KPiA+DQo+ID4gIHN0cnVjdCBjbG9ja2dlbjsNCj4gPg0KPiA+IEBAIC01NzAsNiArNTcw
LDE3IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3QgY2xvY2tnZW5fY2hpcGluZm8gY2hpcGluZm9bXSA9
IHsNCj4gPiAgCQkuZmxhZ3MgPSBDR19WRVIzIHwgQ0dfTElUVExFX0VORElBTiwNCj4gPiAgCX0s
DQo+ID4gIAl7DQo+ID4gKwkJLmNvbXBhdCA9ICJmc2wsbHgyMTYwYS1jbG9ja2dlbiIsDQo+ID4g
KwkJLmNtdXhfZ3JvdXBzID0gew0KPiA+ICsJCQkmY2xvY2tnZW4yX2NtdXhfY2dhMTIsICZjbG9j
a2dlbjJfY211eF9jZ2INCj4gPiArCQl9LA0KPiA+ICsJCS5jbXV4X3RvX2dyb3VwID0gew0KPiA+
ICsJCQkwLCAwLCAwLCAwLCAxLCAxLCAxLCAxLCAtMQ0KPiA+ICsJCX0sDQo+ID4gKwkJLnBsbF9t
YXNrID0gMHgzNywNCj4gPiArCQkuZmxhZ3MgPSBDR19WRVIzIHwgQ0dfTElUVExFX0VORElBTiwN
Cj4gPiArCX0sDQo+IA0KPiBXaHkgYXJlIHlvdSBpbmNyZWFzaW5nIE5VTV9DTVVYIGJleW9uZCA4
IGZvciBhIGNoaXAgdGhhdCBvbmx5IGhhcyA4DQo+IGVudHJpZXMgaW4gY211eF90b19ncm91cD8N
CkNvbmZpZ3VyYXRpb24gaXMgMTYgY29yZXMsOCBjbHVzdGVyIHdpdGggMiBjb3JlcyBpbiBlYWNo
IGNsdXN0ZXINCj4gDQo+IC1TY290dA0KDQo=
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-30 7:36 ` Vabhav Sharma
@ 2018-08-30 17:39 ` Scott Wood
2018-08-30 17:42 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2018-08-30 17:39 UTC (permalink / raw)
To: Vabhav Sharma, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, Andy Tang, Udit Kumar, linux@armlinux.org.uk,
Varun Sethi
On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > -----Original Message-----
> > From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> > owner@vger.kernel.org> On Behalf Of Scott Wood
> > Sent: Wednesday, August 29, 2018 5:49 AM
> > To: Vabhav Sharma <vabhav.sharma@nxp.com>; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; robh+dt@kernel.org;
> > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org; linux-arm-
> > kernel@lists.infradead.org; mturquette@baylibre.com; sboyd@kernel.org;
> > rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> > linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> > catalin.marinas@arm.com; will.deacon@arm.com;
> > gregkh@linuxfoundation.org; arnd@arndb.de;
> > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> > <andy.tang@nxp.com>; Udit Kumar <udit.kumar@nxp.com>;
> > linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> >
> > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > >
> > > Add clockgen support for lx2160a.
> > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > >
> > > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > > ---
> > > drivers/clk/clk-qoriq.c | 14 +++++++++++++-
> > > drivers/cpufreq/qoriq-cpufreq.c | 1 +
> > > 2 files changed, 14 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > > 3a1812f..fc6e308 100644
> > > --- a/drivers/clk/clk-qoriq.c
> > > +++ b/drivers/clk/clk-qoriq.c
> > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo { };
> > >
> > > #define NUM_HWACCEL 5
> > > -#define NUM_CMUX 8
> > > +#define NUM_CMUX 16
> > >
> > > struct clockgen;
> > >
> > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] =
> > > {
> > > .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > },
> > > {
> > > + .compat = "fsl,lx2160a-clockgen",
> > > + .cmux_groups = {
> > > + &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > + },
> > > + .cmux_to_group = {
> > > + 0, 0, 0, 0, 1, 1, 1, 1, -1
> > > + },
> > > + .pll_mask = 0x37,
> > > + .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > + },
> >
> > Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> > entries in cmux_to_group?
>
> Configuration is 16 cores,8 cluster with 2 cores in each cluster
So? This is about cmuxes, not cores. You're increasing the array without
ever using the new size.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-30 17:39 ` Scott Wood
@ 2018-08-30 17:42 ` Scott Wood
2018-08-31 6:12 ` Andy Tang
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2018-08-30 17:42 UTC (permalink / raw)
To: Vabhav Sharma, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, Andy Tang, Udit Kumar, linux@armlinux.org.uk,
Varun Sethi
On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > -----Original Message-----
> > > From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> > > owner@vger.kernel.org> On Behalf Of Scott Wood
> > > Sent: Wednesday, August 29, 2018 5:49 AM
> > > To: Vabhav Sharma <vabhav.sharma@nxp.com>; linux-
> > > kernel@vger.kernel.org; devicetree@vger.kernel.org; robh+dt@kernel.org;
> > > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org; linux-arm-
> > > kernel@lists.infradead.org; mturquette@baylibre.com; sboyd@kernel.org;
> > > rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> > > linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> > > catalin.marinas@arm.com; will.deacon@arm.com;
> > > gregkh@linuxfoundation.org; arnd@arndb.de;
> > > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> > > <andy.tang@nxp.com>; Udit Kumar <udit.kumar@nxp.com>;
> > > linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>
> > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > > lx2160a
> > >
> > > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > >
> > > > Add clockgen support for lx2160a.
> > > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > >
> > > > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > > > ---
> > > > drivers/clk/clk-qoriq.c | 14 +++++++++++++-
> > > > drivers/cpufreq/qoriq-cpufreq.c | 1 +
> > > > 2 files changed, 14 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > > > 3a1812f..fc6e308 100644
> > > > --- a/drivers/clk/clk-qoriq.c
> > > > +++ b/drivers/clk/clk-qoriq.c
> > > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo { };
> > > >
> > > > #define NUM_HWACCEL 5
> > > > -#define NUM_CMUX 8
> > > > +#define NUM_CMUX 16
> > > >
> > > > struct clockgen;
> > > >
> > > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[]
> > > > =
> > > > {
> > > > .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > },
> > > > {
> > > > + .compat = "fsl,lx2160a-clockgen",
> > > > + .cmux_groups = {
> > > > + &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > > + },
> > > > + .cmux_to_group = {
> > > > + 0, 0, 0, 0, 1, 1, 1, 1, -1
> > > > + },
> > > > + .pll_mask = 0x37,
> > > > + .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > + },
> > >
> > > Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> > > entries in cmux_to_group?
> >
> > Configuration is 16 cores,8 cluster with 2 cores in each cluster
>
> So? This is about cmuxes, not cores. You're increasing the array without
> ever using the new size.
Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator, because
the array was of length 8. Probably the array should be changed to NUM_CMUX+1
so every array can be -1 terminated.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-30 17:42 ` Scott Wood
@ 2018-08-31 6:12 ` Andy Tang
2018-08-31 20:28 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: Andy Tang @ 2018-08-31 6:12 UTC (permalink / raw)
To: Scott Wood, Vabhav Sharma, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, linux@armlinux.org.uk, Varun Sethi,
Udit Kumar
SGkgU2NvdHQsDQoNClBsZWFzZSBzZWUgbXkgcmVwbGF5IGlubGluZS4NCg0KPiAtLS0tLU9yaWdp
bmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBsaW51eC1hcm0ta2VybmVsIDxsaW51eC1hcm0ta2Vy
bmVsLWJvdW5jZXNAbGlzdHMuaW5mcmFkZWFkLm9yZz4NCj4gT24gQmVoYWxmIE9mIFNjb3R0IFdv
b2QNCj4gU2VudDogMjAxOMTqONTCMzHI1SAxOjQzDQo+IFRvOiBWYWJoYXYgU2hhcm1hIDx2YWJo
YXYuc2hhcm1hQG54cC5jb20+Ow0KPiBsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnOyBkZXZp
Y2V0cmVlQHZnZXIua2VybmVsLm9yZzsNCj4gcm9iaCtkdEBrZXJuZWwub3JnOyBtYXJrLnJ1dGxh
bmRAYXJtLmNvbTsNCj4gbGludXhwcGMtZGV2QGxpc3RzLm96bGFicy5vcmc7IGxpbnV4LWFybS1r
ZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZzsNCj4gbXR1cnF1ZXR0ZUBiYXlsaWJyZS5jb207IHNi
b3lkQGtlcm5lbC5vcmc7IHJqd0Byand5c29ja2kubmV0Ow0KPiB2aXJlc2gua3VtYXJAbGluYXJv
Lm9yZzsgbGludXgtY2xrQHZnZXIua2VybmVsLm9yZzsNCj4gbGludXgtcG1Admdlci5rZXJuZWwu
b3JnOyBsaW51eC1rZXJuZWwtb3duZXJAdmdlci5rZXJuZWwub3JnOw0KPiBjYXRhbGluLm1hcmlu
YXNAYXJtLmNvbTsgd2lsbC5kZWFjb25AYXJtLmNvbTsNCj4gZ3JlZ2toQGxpbnV4Zm91bmRhdGlv
bi5vcmc7IGFybmRAYXJuZGIuZGU7DQo+IGtzdGV3YXJ0QGxpbnV4Zm91bmRhdGlvbi5vcmc7IHlh
bWFkYS5tYXNhaGlyb0Bzb2Npb25leHQuY29tDQo+IENjOiBZb2dlc2ggTmFyYXlhbiBHYXVyIDx5
b2dlc2huYXJheWFuLmdhdXJAbnhwLmNvbT47IEFuZHkgVGFuZw0KPiA8YW5keS50YW5nQG54cC5j
b20+OyBsaW51eEBhcm1saW51eC5vcmcudWs7IFZhcnVuIFNldGhpDQo+IDxWLlNldGhpQG54cC5j
b20+OyBVZGl0IEt1bWFyIDx1ZGl0Lmt1bWFyQG54cC5jb20+DQo+IFN1YmplY3Q6IFJlOiBbUEFU
Q0ggMy81XSBkcml2ZXJzOiBjbGstcW9yaXE6IEFkZCBjbG9ja2dlbiBzdXBwb3J0IGZvcg0KPiBs
eDIxNjBhDQo+IA0KPiBPbiBUaHUsIDIwMTgtMDgtMzAgYXQgMTI6MzkgLTA1MDAsIFNjb3R0IFdv
b2Qgd3JvdGU6DQo+ID4gT24gVGh1LCAyMDE4LTA4LTMwIGF0IDA3OjM2ICswMDAwLCBWYWJoYXYg
U2hhcm1hIHdyb3RlOg0KPiA+ID4gPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+ID4g
PiBGcm9tOiBsaW51eC1rZXJuZWwtb3duZXJAdmdlci5rZXJuZWwub3JnIDxsaW51eC1rZXJuZWwt
DQo+ID4gPiA+IG93bmVyQHZnZXIua2VybmVsLm9yZz4gT24gQmVoYWxmIE9mIFNjb3R0IFdvb2QN
Cj4gPiA+ID4gU2VudDogV2VkbmVzZGF5LCBBdWd1c3QgMjksIDIwMTggNTo0OSBBTQ0KPiA+ID4g
PiBUbzogVmFiaGF2IFNoYXJtYSA8dmFiaGF2LnNoYXJtYUBueHAuY29tPjsgbGludXgtDQo+ID4g
PiA+IGtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7IGRldmljZXRyZWVAdmdlci5rZXJuZWwub3JnOw0K
PiA+ID4gPiByb2JoK2R0QGtlcm5lbC5vcmc7IG1hcmsucnV0bGFuZEBhcm0uY29tOw0KPiA+ID4g
PiBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZzsgbGludXgtYXJtLQ0KPiA+ID4gPiBrZXJu
ZWxAbGlzdHMuaW5mcmFkZWFkLm9yZzsgbXR1cnF1ZXR0ZUBiYXlsaWJyZS5jb207DQo+ID4gPiA+
IHNib3lkQGtlcm5lbC5vcmc7IHJqd0Byand5c29ja2kubmV0OyB2aXJlc2gua3VtYXJAbGluYXJv
Lm9yZzsNCj4gPiA+ID4gbGludXgtY2xrQHZnZXIua2VybmVsLm9yZzsgbGludXgtcG1Admdlci5r
ZXJuZWwub3JnOw0KPiA+ID4gPiBsaW51eC1rZXJuZWwtb3duZXJAdmdlci5rZXJuZWwub3JnOw0K
PiA+ID4gPiBjYXRhbGluLm1hcmluYXNAYXJtLmNvbTsgd2lsbC5kZWFjb25AYXJtLmNvbTsNCj4g
PiA+ID4gZ3JlZ2toQGxpbnV4Zm91bmRhdGlvbi5vcmc7IGFybmRAYXJuZGIuZGU7DQo+ID4gPiA+
IGtzdGV3YXJ0QGxpbnV4Zm91bmRhdGlvbi5vcmc7IHlhbWFkYS5tYXNhaGlyb0Bzb2Npb25leHQu
Y29tDQo+ID4gPiA+IENjOiBZb2dlc2ggTmFyYXlhbiBHYXVyIDx5b2dlc2huYXJheWFuLmdhdXJA
bnhwLmNvbT47IEFuZHkNCj4gVGFuZw0KPiA+ID4gPiA8YW5keS50YW5nQG54cC5jb20+OyBVZGl0
IEt1bWFyIDx1ZGl0Lmt1bWFyQG54cC5jb20+Ow0KPiA+ID4gPiBsaW51eEBhcm1saW51eC5vcmcu
dWs7IFZhcnVuIFNldGhpIDxWLlNldGhpQG54cC5jb20+DQo+ID4gPiA+IFN1YmplY3Q6IFJlOiBb
UEFUQ0ggMy81XSBkcml2ZXJzOiBjbGstcW9yaXE6IEFkZCBjbG9ja2dlbiBzdXBwb3J0DQo+ID4g
PiA+IGZvciBseDIxNjBhDQo+ID4gPiA+DQo+ID4gPiA+IE9uIE1vbiwgMjAxOC0wOC0yMCBhdCAx
MjoxNyArMDUzMCwgVmFiaGF2IFNoYXJtYSB3cm90ZToNCj4gPiA+ID4gPiBGcm9tOiBZb2dlc2gg
R2F1ciA8eW9nZXNobmFyYXlhbi5nYXVyQG54cC5jb20+DQo+ID4gPiA+ID4NCj4gPiA+ID4gPiBB
ZGQgY2xvY2tnZW4gc3VwcG9ydCBmb3IgbHgyMTYwYS4NCj4gPiA+ID4gPiBBZGRlZCBlbnRyeSBm
b3IgY29tcGF0ICdmc2wsbHgyMTYwYS1jbG9ja2dlbicuDQo+ID4gPiA+ID4gQXMgTFgyMTYwQSBp
cyAxNiBjb3JlLCBzbyBtb2RpZmllZCB2YWx1ZSBmb3IgTlVNX0NNVVgNCj4gPiA+ID4gPg0KPiA+
ID4gPiA+IFNpZ25lZC1vZmYtYnk6IFRhbmcgWXVhbnRpYW4gPGFuZHkudGFuZ0BueHAuY29tPg0K
PiA+ID4gPiA+IFNpZ25lZC1vZmYtYnk6IFlvZ2VzaCBHYXVyIDx5b2dlc2huYXJheWFuLmdhdXJA
bnhwLmNvbT4NCj4gPiA+ID4gPiBTaWduZWQtb2ZmLWJ5OiBWYWJoYXYgU2hhcm1hIDx2YWJoYXYu
c2hhcm1hQG54cC5jb20+DQo+ID4gPiA+ID4gLS0tDQo+ID4gPiA+ID4gIGRyaXZlcnMvY2xrL2Ns
ay1xb3JpcS5jICAgICAgICAgfCAxNCArKysrKysrKysrKysrLQ0KPiA+ID4gPiA+ICBkcml2ZXJz
L2NwdWZyZXEvcW9yaXEtY3B1ZnJlcS5jIHwgIDEgKw0KPiA+ID4gPiA+ICAyIGZpbGVzIGNoYW5n
ZWQsIDE0IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkNCj4gPiA+ID4gPg0KPiA+ID4gPiA+
IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsay9jbGstcW9yaXEuYyBiL2RyaXZlcnMvY2xrL2Nsay1x
b3JpcS5jDQo+ID4gPiA+ID4gaW5kZXgNCj4gPiA+ID4gPiAzYTE4MTJmLi5mYzZlMzA4IDEwMDY0
NA0KPiA+ID4gPiA+IC0tLSBhL2RyaXZlcnMvY2xrL2Nsay1xb3JpcS5jDQo+ID4gPiA+ID4gKysr
IGIvZHJpdmVycy9jbGsvY2xrLXFvcmlxLmMNCj4gPiA+ID4gPiBAQCAtNjAsNyArNjAsNyBAQCBz
dHJ1Y3QgY2xvY2tnZW5fbXV4aW5mbyB7ICB9Ow0KPiA+ID4gPiA+DQo+ID4gPiA+ID4gICNkZWZp
bmUgTlVNX0hXQUNDRUwJNQ0KPiA+ID4gPiA+IC0jZGVmaW5lIE5VTV9DTVVYCTgNCj4gPiA+ID4g
PiArI2RlZmluZSBOVU1fQ01VWAkxNg0KPiA+ID4gPiA+DQo+ID4gPiA+ID4gIHN0cnVjdCBjbG9j
a2dlbjsNCj4gPiA+ID4gPg0KPiA+ID4gPiA+IEBAIC01NzAsNiArNTcwLDE3IEBAIHN0YXRpYyBj
b25zdCBzdHJ1Y3QgY2xvY2tnZW5fY2hpcGluZm8NCj4gPiA+ID4gPiBjaGlwaW5mb1tdID0gew0K
PiA+ID4gPiA+ICAJCS5mbGFncyA9IENHX1ZFUjMgfCBDR19MSVRUTEVfRU5ESUFOLA0KPiA+ID4g
PiA+ICAJfSwNCj4gPiA+ID4gPiAgCXsNCj4gPiA+ID4gPiArCQkuY29tcGF0ID0gImZzbCxseDIx
NjBhLWNsb2NrZ2VuIiwNCj4gPiA+ID4gPiArCQkuY211eF9ncm91cHMgPSB7DQo+ID4gPiA+ID4g
KwkJCSZjbG9ja2dlbjJfY211eF9jZ2ExMiwgJmNsb2NrZ2VuMl9jbXV4X2NnYg0KPiA+ID4gPiA+
ICsJCX0sDQo+ID4gPiA+ID4gKwkJLmNtdXhfdG9fZ3JvdXAgPSB7DQo+ID4gPiA+ID4gKwkJCTAs
IDAsIDAsIDAsIDEsIDEsIDEsIDEsIC0xDQo+ID4gPiA+ID4gKwkJfSwNCj4gPiA+ID4gPiArCQku
cGxsX21hc2sgPSAweDM3LA0KPiA+ID4gPiA+ICsJCS5mbGFncyA9IENHX1ZFUjMgfCBDR19MSVRU
TEVfRU5ESUFOLA0KPiA+ID4gPiA+ICsJfSwNCj4gPiA+ID4NCj4gPiA+ID4gV2h5IGFyZSB5b3Ug
aW5jcmVhc2luZyBOVU1fQ01VWCBiZXlvbmQgOCBmb3IgYSBjaGlwIHRoYXQgb25seQ0KPiBoYXMN
Cj4gPiA+ID4gOCBlbnRyaWVzIGluIGNtdXhfdG9fZ3JvdXA/DQo+ID4gPg0KPiA+ID4gQ29uZmln
dXJhdGlvbiBpcyAxNiBjb3Jlcyw4IGNsdXN0ZXIgd2l0aCAyIGNvcmVzIGluIGVhY2ggY2x1c3Rl
cg0KPiA+DQo+ID4gU28/ICBUaGlzIGlzIGFib3V0IGNtdXhlcywgbm90IGNvcmVzLiAgWW91J3Jl
IGluY3JlYXNpbmcgdGhlIGFycmF5DQo+ID4gd2l0aG91dCBldmVyIHVzaW5nIHRoZSBuZXcgc2l6
ZS4NCj4gDQo+IE9oLCBhbmQgeW91IGFsc28gYnJva2UgcDQwODAgd2hpY2ggaGFzIDggY211eGVz
IGJ1dCBubyAtMSB0ZXJtaW5hdG9yLA0KPiBiZWNhdXNlIHRoZSBhcnJheSB3YXMgb2YgbGVuZ3Ro
IDguICBQcm9iYWJseSB0aGUgYXJyYXkgc2hvdWxkIGJlIGNoYW5nZWQNCj4gdG8gTlVNX0NNVVgr
MSBzbyBldmVyeSBhcnJheSBjYW4gYmUgLTEgdGVybWluYXRlZC4NCj4gDQpbQW5keV0gSG93IGFi
b3V0IHdlIGFkZCAtMSB0ZXJtaW5hdG9yIHRvIHA0MDgwIGFuZCBpbmNyZWFzZSBOVU1fQ01VWCB0
byAxNj8NCldlIGRvbid0IHdhbnQgdG8gaW5jcmVhc2UgTlVNX0NNVVggZWFjaCB0aW1lIG5ldyBz
b2Mgd2l0aCBtb3JlIGNtdXhlcyBhZGRlZC4NCg0KQlIsDQpBbmR5IFRhbmcNCg0KPiAtU2NvdHQN
Cj4gDQo+IA0KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
Xw0KPiBsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdA0KPiBsaW51eC1hcm0ta2VybmVsQGxp
c3RzLmluZnJhZGVhZC5vcmcNCj4gaHR0cHM6Ly9lbWVhMDEuc2FmZWxpbmtzLnByb3RlY3Rpb24u
b3V0bG9vay5jb20vP3VybD1odHRwJTNBJTJGJTJGbGlzdA0KPiBzLmluZnJhZGVhZC5vcmclMkZt
YWlsbWFuJTJGbGlzdGluZm8lMkZsaW51eC1hcm0ta2VybmVsJmFtcDtkYXRhPTAyDQo+ICU3QzAx
JTdDYW5keS50YW5nJTQwbnhwLmNvbSU3Qzk2M2QwY2RmNDk5NjQ1MzllYTQ0MDhkNjBlYTA2DQo+
IDYzYiU3QzY4NmVhMWQzYmMyYjRjNmZhOTJjZDk5YzVjMzAxNjM1JTdDMCU3QzAlN0M2MzY3MTI0
Nw0KPiA5NDE0NTYxMTAxJmFtcDtzZGF0YT1yWlklMkY1SlAwVEJaUkxyJTJCcDZxYUc0b1NRZDhm
c052aXo5MkFZDQo+IDNJb0xUT3clM0QmYW1wO3Jlc2VydmVkPTANCg==
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-31 6:12 ` Andy Tang
@ 2018-08-31 20:28 ` Scott Wood
2018-09-03 1:17 ` Andy Tang
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2018-08-31 20:28 UTC (permalink / raw)
To: Andy Tang, Vabhav Sharma, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, linux@armlinux.org.uk, Varun Sethi,
Udit Kumar
On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> Hi Scott,
>
> Please see my replay inline.
>
> > -----Original Message-----
> > From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org>
> > On Behalf Of Scott Wood
> > Sent: 2018年8月31日 1:43
> > To: Vabhav Sharma <vabhav.sharma@nxp.com>;
> > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> > robh+dt@kernel.org; mark.rutland@arm.com;
> > linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> > mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> > viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> > linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> > catalin.marinas@arm.com; will.deacon@arm.com;
> > gregkh@linuxfoundation.org; arnd@arndb.de;
> > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> > <andy.tang@nxp.com>; linux@armlinux.org.uk; Varun Sethi
> > <V.Sethi@nxp.com>; Udit Kumar <udit.kumar@nxp.com>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> >
> > On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > >
> > > > > Why are you increasing NUM_CMUX beyond 8 for a chip that only
> >
> > has
> > > > > 8 entries in cmux_to_group?
> > > >
> > > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> > >
> > > So? This is about cmuxes, not cores. You're increasing the array
> > > without ever using the new size.
> >
> > Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator,
> > because the array was of length 8. Probably the array should be changed
> > to NUM_CMUX+1 so every array can be -1 terminated.
> >
>
> [Andy] How about we add -1 terminator to p4080 and increase NUM_CMUX to 16?
Why 16? What does such a change have to do with this chip, which according to
the rest of the patch has 8 cmuxes?
> We don't want to increase NUM_CMUX each time new soc with more cmuxes added.
You don't want to have to make a trivial change each time you exceed a limit
that has yet to be exceeded once since NUM_CMUX was added? This isn't ABI or
in any other way hard to change. It's right in the same file as the chip
description you'd be adding.
And even if a chip did come along with 16 cmuxes, you'd then need to increase
the array to 17 to hold the -1 if you don't want to leave a situation like the
p4080 is in now, where a chip's cmux array could be broken by increasing
NUM_CMUX further.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-08-31 20:28 ` Scott Wood
@ 2018-09-03 1:17 ` Andy Tang
2018-09-03 20:33 ` Scott Wood
0 siblings, 1 reply; 23+ messages in thread
From: Andy Tang @ 2018-09-03 1:17 UTC (permalink / raw)
To: Scott Wood, Vabhav Sharma, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, linux@armlinux.org.uk, Udit Kumar,
Varun Sethi
SGkgU2NvdHQsDQoNClBsZWFzZSBzZWUgbXkgcmVwbGF5IGluIGxpbmUuDQoNCj4gLS0tLS1Pcmln
aW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTGludXhwcGMtZGV2DQo+IDxsaW51eHBwYy1kZXYt
Ym91bmNlcytiMjk5ODM9ZnJlZXNjYWxlLmNvbUBsaXN0cy5vemxhYnMub3JnPiBPbg0KPiBCZWhh
bGYgT2YgU2NvdHQgV29vZA0KPiBTZW50OiAyMDE45bm0OeaciDHml6UgNDoyOQ0KPiBUbzogQW5k
eSBUYW5nIDxhbmR5LnRhbmdAbnhwLmNvbT47IFZhYmhhdiBTaGFybWENCj4gPHZhYmhhdi5zaGFy
bWFAbnhwLmNvbT47IGxpbnV4LWtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7DQo+IGRldmljZXRyZWVA
dmdlci5rZXJuZWwub3JnOyByb2JoK2R0QGtlcm5lbC5vcmc7DQo+IG1hcmsucnV0bGFuZEBhcm0u
Y29tOyBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZzsNCj4gbGludXgtYXJtLWtlcm5lbEBs
aXN0cy5pbmZyYWRlYWQub3JnOyBtdHVycXVldHRlQGJheWxpYnJlLmNvbTsNCj4gc2JveWRAa2Vy
bmVsLm9yZzsgcmp3QHJqd3lzb2NraS5uZXQ7IHZpcmVzaC5rdW1hckBsaW5hcm8ub3JnOw0KPiBs
aW51eC1jbGtAdmdlci5rZXJuZWwub3JnOyBsaW51eC1wbUB2Z2VyLmtlcm5lbC5vcmc7DQo+IGxp
bnV4LWtlcm5lbC1vd25lckB2Z2VyLmtlcm5lbC5vcmc7IGNhdGFsaW4ubWFyaW5hc0Bhcm0uY29t
Ow0KPiB3aWxsLmRlYWNvbkBhcm0uY29tOyBncmVna2hAbGludXhmb3VuZGF0aW9uLm9yZzsgYXJu
ZEBhcm5kYi5kZTsNCj4ga3N0ZXdhcnRAbGludXhmb3VuZGF0aW9uLm9yZzsgeWFtYWRhLm1hc2Fo
aXJvQHNvY2lvbmV4dC5jb20NCj4gQ2M6IFlvZ2VzaCBOYXJheWFuIEdhdXIgPHlvZ2VzaG5hcmF5
YW4uZ2F1ckBueHAuY29tPjsNCj4gbGludXhAYXJtbGludXgub3JnLnVrOyBVZGl0IEt1bWFyIDx1
ZGl0Lmt1bWFyQG54cC5jb20+OyBWYXJ1biBTZXRoaQ0KPiA8Vi5TZXRoaUBueHAuY29tPg0KPiBT
dWJqZWN0OiBSZTogW1BBVENIIDMvNV0gZHJpdmVyczogY2xrLXFvcmlxOiBBZGQgY2xvY2tnZW4g
c3VwcG9ydCBmb3INCj4gbHgyMTYwYQ0KPiANCj4gT24gRnJpLCAyMDE4LTA4LTMxIGF0IDA2OjEy
ICswMDAwLCBBbmR5IFRhbmcgd3JvdGU6DQo+ID4gSGkgU2NvdHQsDQo+ID4NCj4gPiBQbGVhc2Ug
c2VlIG15IHJlcGxheSBpbmxpbmUuDQo+ID4NCj4gPiA+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t
LS0tDQo+ID4gPiBGcm9tOiBsaW51eC1hcm0ta2VybmVsDQo+ID4gPiA8bGludXgtYXJtLWtlcm5l
bC1ib3VuY2VzQGxpc3RzLmluZnJhZGVhZC5vcmc+DQo+ID4gPiBPbiBCZWhhbGYgT2YgU2NvdHQg
V29vZA0KPiA+ID4gU2VudDogMjAxOOW5tDjmnIgzMeaXpSAxOjQzDQo+ID4gPiBUbzogVmFiaGF2
IFNoYXJtYSA8dmFiaGF2LnNoYXJtYUBueHAuY29tPjsNCj4gPiA+IGxpbnV4LWtlcm5lbEB2Z2Vy
Lmtlcm5lbC5vcmc7IGRldmljZXRyZWVAdmdlci5rZXJuZWwub3JnOw0KPiA+ID4gcm9iaCtkdEBr
ZXJuZWwub3JnOyBtYXJrLnJ1dGxhbmRAYXJtLmNvbTsNCj4gPiA+IGxpbnV4cHBjLWRldkBsaXN0
cy5vemxhYnMub3JnOyBsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmc7DQo+ID4g
PiBtdHVycXVldHRlQGJheWxpYnJlLmNvbTsgc2JveWRAa2VybmVsLm9yZzsgcmp3QHJqd3lzb2Nr
aS5uZXQ7DQo+ID4gPiB2aXJlc2gua3VtYXJAbGluYXJvLm9yZzsgbGludXgtY2xrQHZnZXIua2Vy
bmVsLm9yZzsNCj4gPiA+IGxpbnV4LXBtQHZnZXIua2VybmVsLm9yZzsgbGludXgta2VybmVsLW93
bmVyQHZnZXIua2VybmVsLm9yZzsNCj4gPiA+IGNhdGFsaW4ubWFyaW5hc0Bhcm0uY29tOyB3aWxs
LmRlYWNvbkBhcm0uY29tOw0KPiA+ID4gZ3JlZ2toQGxpbnV4Zm91bmRhdGlvbi5vcmc7IGFybmRA
YXJuZGIuZGU7DQo+ID4gPiBrc3Rld2FydEBsaW51eGZvdW5kYXRpb24ub3JnOyB5YW1hZGEubWFz
YWhpcm9Ac29jaW9uZXh0LmNvbQ0KPiA+ID4gQ2M6IFlvZ2VzaCBOYXJheWFuIEdhdXIgPHlvZ2Vz
aG5hcmF5YW4uZ2F1ckBueHAuY29tPjsgQW5keSBUYW5nDQo+ID4gPiA8YW5keS50YW5nQG54cC5j
b20+OyBsaW51eEBhcm1saW51eC5vcmcudWs7IFZhcnVuIFNldGhpDQo+ID4gPiA8Vi5TZXRoaUBu
eHAuY29tPjsgVWRpdCBLdW1hciA8dWRpdC5rdW1hckBueHAuY29tPg0KPiA+ID4gU3ViamVjdDog
UmU6IFtQQVRDSCAzLzVdIGRyaXZlcnM6IGNsay1xb3JpcTogQWRkIGNsb2NrZ2VuIHN1cHBvcnQN
Cj4gPiA+IGZvciBseDIxNjBhDQo+ID4gPg0KPiA+ID4gT24gVGh1LCAyMDE4LTA4LTMwIGF0IDEy
OjM5IC0wNTAwLCBTY290dCBXb29kIHdyb3RlOg0KPiA+ID4gPiBPbiBUaHUsIDIwMTgtMDgtMzAg
YXQgMDc6MzYgKzAwMDAsIFZhYmhhdiBTaGFybWEgd3JvdGU6DQo+ID4gPiA+ID4gPg0KPiA+ID4g
PiA+ID4gV2h5IGFyZSB5b3UgaW5jcmVhc2luZyBOVU1fQ01VWCBiZXlvbmQgOCBmb3IgYSBjaGlw
IHRoYXQNCj4gb25seQ0KPiA+ID4NCj4gPiA+IGhhcw0KPiA+ID4gPiA+ID4gOCBlbnRyaWVzIGlu
IGNtdXhfdG9fZ3JvdXA/DQo+ID4gPiA+ID4NCj4gPiA+ID4gPiBDb25maWd1cmF0aW9uIGlzIDE2
IGNvcmVzLDggY2x1c3RlciB3aXRoIDIgY29yZXMgaW4gZWFjaCBjbHVzdGVyDQo+ID4gPiA+DQo+
ID4gPiA+IFNvPyAgVGhpcyBpcyBhYm91dCBjbXV4ZXMsIG5vdCBjb3Jlcy4gIFlvdSdyZSBpbmNy
ZWFzaW5nIHRoZSBhcnJheQ0KPiA+ID4gPiB3aXRob3V0IGV2ZXIgdXNpbmcgdGhlIG5ldyBzaXpl
Lg0KPiA+ID4NCj4gPiA+IE9oLCBhbmQgeW91IGFsc28gYnJva2UgcDQwODAgd2hpY2ggaGFzIDgg
Y211eGVzIGJ1dCBubyAtMQ0KPiA+ID4gdGVybWluYXRvciwgYmVjYXVzZSB0aGUgYXJyYXkgd2Fz
IG9mIGxlbmd0aCA4LiAgUHJvYmFibHkgdGhlIGFycmF5DQo+ID4gPiBzaG91bGQgYmUgY2hhbmdl
ZCB0byBOVU1fQ01VWCsxIHNvIGV2ZXJ5IGFycmF5IGNhbiBiZSAtMQ0KPiB0ZXJtaW5hdGVkLg0K
PiA+ID4NCj4gPg0KPiA+IFtBbmR5XSBIb3cgYWJvdXQgd2UgYWRkIC0xIHRlcm1pbmF0b3IgdG8g
cDQwODAgYW5kIGluY3JlYXNlDQo+IE5VTV9DTVVYIHRvIDE2Pw0KPiANCj4gV2h5IDE2PyAgV2hh
dCBkb2VzIHN1Y2ggYSBjaGFuZ2UgaGF2ZSB0byBkbyB3aXRoIHRoaXMgY2hpcCwgd2hpY2gNCj4g
YWNjb3JkaW5nIHRvIHRoZSByZXN0IG9mIHRoZSBwYXRjaCBoYXMgOCBjbXV4ZXM/DQpbQW5keV0g
TlVNX0NNVVggaXMgYSBsaW1pdGF0aW9uIG51bWJlci4gV2UgYmV0dGVyIGdpdmUgaXQgYW4gZXh0
cmEgYnVmZmVyLCBub3QgZXhhY3RseSBlcXVhbCB0byB0aGUgbGltaXRhdGlvbi4NCjE2IGlzIHRo
ZSBsaW1pdGF0aW9uIG51bWJlciB3aXRoIGV4dHJhIGJ1ZmZlci4NCg0KPiANCj4gPiBXZSBkb24n
dCB3YW50IHRvIGluY3JlYXNlIE5VTV9DTVVYIGVhY2ggdGltZSBuZXcgc29jIHdpdGggbW9yZQ0K
PiBjbXV4ZXMgYWRkZWQuDQo+IA0KPiBZb3UgZG9uJ3Qgd2FudCB0byBoYXZlIHRvIG1ha2UgYSB0
cml2aWFsIGNoYW5nZSBlYWNoIHRpbWUgeW91IGV4Y2VlZCBhDQo+IGxpbWl0IHRoYXQgaGFzIHll
dCB0byBiZSBleGNlZWRlZCBvbmNlIHNpbmNlIE5VTV9DTVVYIHdhcyBhZGRlZD8NCj4gVGhpcyBp
c24ndCBBQkkgb3IgaW4gYW55IG90aGVyIHdheSBoYXJkIHRvIGNoYW5nZS4gIEl0J3MgcmlnaHQg
aW4gdGhlIHNhbWUgZmlsZQ0KPiBhcyB0aGUgY2hpcCBkZXNjcmlwdGlvbiB5b3UnZCBiZSBhZGRp
bmcuDQo+IA0KPiBBbmQgZXZlbiBpZiBhIGNoaXAgZGlkIGNvbWUgYWxvbmcgd2l0aCAxNiBjbXV4
ZXMsIHlvdSdkIHRoZW4gbmVlZCB0bw0KPiBpbmNyZWFzZSB0aGUgYXJyYXkgdG8gMTcgdG8gaG9s
ZCB0aGUgLTEgaWYgeW91IGRvbid0IHdhbnQgdG8gbGVhdmUgYSBzaXR1YXRpb24NCj4gbGlrZSB0
aGUNCj4gcDQwODAgaXMgaW4gbm93LCB3aGVyZSBhIGNoaXAncyBjbXV4IGFycmF5IGNvdWxkIGJl
IGJyb2tlbiBieSBpbmNyZWFzaW5nDQo+IE5VTV9DTVVYIGZ1cnRoZXIuDQo+IA0KW0FuZHldIEFk
ZGluZyBidWZmZXIgdG8gYSBsaW1pdGF0aW9uIG51bWJlciBpcyBhbHdheXMgYSBnb29kIGhhYml0
IHdoZW4gY29kaW5nLiBXZSBvZnRlbiBmb3JnZXQgdG8gaW5jcmVhc2UgdGhpcyB2YWx1ZSB3aGVu
DQphIG5ldyBjaGlwIHdpdGggbW9yZSBjbXV4ZXMgYWRkZWQuIExpa2UgdGhpcyBwYXRjaCwgd2Ug
ZGlkbid0IGluY3JlYXNlIHRoaXMgdmFsdWUgYXQgZmlyc3QuIFdlIHNwZW50IGEgbG90IG9mIHRp
bWUgZmluZGluZyBvdXQgdGhhdCBOVU1fQ01VWCBuZWVkcyB0byBiZSBpbmNyZWFzZWQgdG9vLg0K
SXQgaXMgYSBwZXJzb25hbCBwcmVmZXJlbmNlIGhvdyB0byBzZXQgdGhpcyB2YWx1ZS4gSSB0aGlu
ayBpdCBpcyBiZXR0ZXIgdG8gaW5jcmVhc2UgaXQgdG8gMTYsIG5vdCBOVU1fQ01VWCsxIGFzIGxv
bmcgYXMgd2UgZml4IHRoZSBQNDA4MCBpc3N1ZQ0KZXZlbiB0aG91Z2ggaXQgaXMgYSB0cml2aWFs
IGNoYW5nZS4gQW5kIEkgYWdyZWUgdGhlIGRlc2NyaXB0aW9uIG5lZWRzIHRvIGJlIHVwZGF0ZWQu
DQoNCkJSLA0KQW5keQ0KDQo+IC1TY290dA0KDQo=
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-09-03 1:17 ` Andy Tang
@ 2018-09-03 20:33 ` Scott Wood
2018-09-04 3:08 ` Andy Tang
0 siblings, 1 reply; 23+ messages in thread
From: Scott Wood @ 2018-09-03 20:33 UTC (permalink / raw)
To: Andy Tang, Vabhav Sharma, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, linux@armlinux.org.uk, Udit Kumar,
Varun Sethi
On Mon, 2018-09-03 at 01:17 +0000, Andy Tang wrote:
> Hi Scott,
>
> Please see my replay in line.
>
> > -----Original Message-----
> > From: Linuxppc-dev
> > <linuxppc-dev-bounces+b29983=freescale.com@lists.ozlabs.org> On
> > Behalf Of Scott Wood
> > Sent: 2018年9月1日 4:29
> > To: Andy Tang <andy.tang@nxp.com>; Vabhav Sharma
> > <vabhav.sharma@nxp.com>; linux-kernel@vger.kernel.org;
> > devicetree@vger.kernel.org; robh+dt@kernel.org;
> > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org;
> > linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> > sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org;
> > linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> > linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> > will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>;
> > linux@armlinux.org.uk; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> > <V.Sethi@nxp.com>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> >
> > On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> > > We don't want to increase NUM_CMUX each time new soc with more
> >
> > cmuxes added.
> >
> > You don't want to have to make a trivial change each time you exceed a
> > limit that has yet to be exceeded once since NUM_CMUX was added?
> > This isn't ABI or in any other way hard to change. It's right in the same
> > file
> > as the chip description you'd be adding.
> >
> > And even if a chip did come along with 16 cmuxes, you'd then need to
> > increase the array to 17 to hold the -1 if you don't want to leave a
> > situation
> > like the
> > p4080 is in now, where a chip's cmux array could be broken by increasing
> > NUM_CMUX further.
> >
>
> [Andy] Adding buffer to a limitation number is always a good habit when
> coding. We often forget to increase this value when
> a new chip with more cmuxes added.
"often"? There has never been a new chip added with more cmuxes than p4080's
8, and if one does come along and you forget, the compiler should complain
about exceeding the array length with a static initializer. This isn't like
an array that is filled with a runtime-determined length.
> Like this patch, we didn't increase this value at first. We spent a lot of
> time finding out that NUM_CMUX needs to be increased too.
Are you talking about some other chip that you haven't sent a patch for yet?
Or is the cmux array for this chip wrong? What specifically did you see
happen "at first"?
> It is a personal preference how to set this value. I think it is better to
> increase it to 16, not NUM_CMUX+1 as long as we fix the P4080 issue
> even though it is a trivial change. And I agree the description needs to be
> updated.
I'm not the clock maintainer, so it's not up to me, but I don't see the point
in setting it to an arbitrary number, and I do not agree that increasing
NUM_CMUX is a suitable replacement for NUM_CMUX+1 in cmux_to_group[], as that
array should be one larger than cmux[] in order to allow every chip to have a
-1 terminator. In any case, any change to NUM_CMUX should be a separate patch
because it's not required for lx2160a support (assuming lx2160a was correctly
described by this patch).
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
2018-09-03 20:33 ` Scott Wood
@ 2018-09-04 3:08 ` Andy Tang
0 siblings, 0 replies; 23+ messages in thread
From: Andy Tang @ 2018-09-04 3:08 UTC (permalink / raw)
To: Scott Wood, Vabhav Sharma, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com
Cc: Yogesh Narayan Gaur, linux@armlinux.org.uk, Varun Sethi,
Udit Kumar
SGkgU2NvdHQsDQoNClBsZWFzZSBzZWUgbXkgcmVwbGF5IGlubGluZS4NCg0KPiAtLS0tLU9yaWdp
bmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBsaW51eC1hcm0ta2VybmVsIDxsaW51eC1hcm0ta2Vy
bmVsLWJvdW5jZXNAbGlzdHMuaW5mcmFkZWFkLm9yZz4NCj4gT24gQmVoYWxmIE9mIFNjb3R0IFdv
b2QNCj4gU2VudDogMjAxOOW5tDnmnIg05pelIDQ6MzQNCj4gVG86IEFuZHkgVGFuZyA8YW5keS50
YW5nQG54cC5jb20+OyBWYWJoYXYgU2hhcm1hDQo+IDx2YWJoYXYuc2hhcm1hQG54cC5jb20+OyBs
aW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnOw0KPiBkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9y
Zzsgcm9iaCtkdEBrZXJuZWwub3JnOw0KPiBtYXJrLnJ1dGxhbmRAYXJtLmNvbTsgbGludXhwcGMt
ZGV2QGxpc3RzLm96bGFicy5vcmc7DQo+IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFk
Lm9yZzsgbXR1cnF1ZXR0ZUBiYXlsaWJyZS5jb207DQo+IHNib3lkQGtlcm5lbC5vcmc7IHJqd0By
and5c29ja2kubmV0OyB2aXJlc2gua3VtYXJAbGluYXJvLm9yZzsNCj4gbGludXgtY2xrQHZnZXIu
a2VybmVsLm9yZzsgbGludXgtcG1Admdlci5rZXJuZWwub3JnOw0KPiBsaW51eC1rZXJuZWwtb3du
ZXJAdmdlci5rZXJuZWwub3JnOyBjYXRhbGluLm1hcmluYXNAYXJtLmNvbTsNCj4gd2lsbC5kZWFj
b25AYXJtLmNvbTsgZ3JlZ2toQGxpbnV4Zm91bmRhdGlvbi5vcmc7IGFybmRAYXJuZGIuZGU7DQo+
IGtzdGV3YXJ0QGxpbnV4Zm91bmRhdGlvbi5vcmc7IHlhbWFkYS5tYXNhaGlyb0Bzb2Npb25leHQu
Y29tDQo+IENjOiBZb2dlc2ggTmFyYXlhbiBHYXVyIDx5b2dlc2huYXJheWFuLmdhdXJAbnhwLmNv
bT47DQo+IGxpbnV4QGFybWxpbnV4Lm9yZy51azsgVmFydW4gU2V0aGkgPFYuU2V0aGlAbnhwLmNv
bT47IFVkaXQgS3VtYXINCj4gPHVkaXQua3VtYXJAbnhwLmNvbT4NCj4gU3ViamVjdDogUmU6IFtQ
QVRDSCAzLzVdIGRyaXZlcnM6IGNsay1xb3JpcTogQWRkIGNsb2NrZ2VuIHN1cHBvcnQgZm9yDQo+
IGx4MjE2MGENCj4gDQo+IE9uIE1vbiwgMjAxOC0wOS0wMyBhdCAwMToxNyArMDAwMCwgQW5keSBU
YW5nIHdyb3RlOg0KPiA+IEhpIFNjb3R0LA0KPiA+DQo+ID4gUGxlYXNlIHNlZSBteSByZXBsYXkg
aW4gbGluZS4NCj4gPg0KPiA+ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiA+IEZy
b206IExpbnV4cHBjLWRldg0KPiA+ID4gPGxpbnV4cHBjLWRldi1ib3VuY2VzK2IyOTk4Mz1mcmVl
c2NhbGUuY29tQGxpc3RzLm96bGFicy5vcmc+IE9uDQo+ID4gPiBCZWhhbGYgT2YgU2NvdHQgV29v
ZA0KPiA+ID4gU2VudDogMjAxOOW5tDnmnIgx5pelIDQ6MjkNCj4gPiA+IFRvOiBBbmR5IFRhbmcg
PGFuZHkudGFuZ0BueHAuY29tPjsgVmFiaGF2IFNoYXJtYQ0KPiA+ID4gPHZhYmhhdi5zaGFybWFA
bnhwLmNvbT47IGxpbnV4LWtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7DQo+ID4gPiBkZXZpY2V0cmVl
QHZnZXIua2VybmVsLm9yZzsgcm9iaCtkdEBrZXJuZWwub3JnOw0KPiA+ID4gbWFyay5ydXRsYW5k
QGFybS5jb207IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOw0KPiA+ID4gbGludXgtYXJt
LWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnOyBtdHVycXVldHRlQGJheWxpYnJlLmNvbTsNCj4g
PiA+IHNib3lkQGtlcm5lbC5vcmc7IHJqd0Byand5c29ja2kubmV0OyB2aXJlc2gua3VtYXJAbGlu
YXJvLm9yZzsNCj4gPiA+IGxpbnV4LWNsa0B2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LXBtQHZnZXIu
a2VybmVsLm9yZzsNCj4gPiA+IGxpbnV4LWtlcm5lbC1vd25lckB2Z2VyLmtlcm5lbC5vcmc7IGNh
dGFsaW4ubWFyaW5hc0Bhcm0uY29tOw0KPiA+ID4gd2lsbC5kZWFjb25AYXJtLmNvbTsgZ3JlZ2to
QGxpbnV4Zm91bmRhdGlvbi5vcmc7IGFybmRAYXJuZGIuZGU7DQo+ID4gPiBrc3Rld2FydEBsaW51
eGZvdW5kYXRpb24ub3JnOyB5YW1hZGEubWFzYWhpcm9Ac29jaW9uZXh0LmNvbQ0KPiA+ID4gQ2M6
IFlvZ2VzaCBOYXJheWFuIEdhdXIgPHlvZ2VzaG5hcmF5YW4uZ2F1ckBueHAuY29tPjsNCj4gPiA+
IGxpbnV4QGFybWxpbnV4Lm9yZy51azsgVWRpdCBLdW1hciA8dWRpdC5rdW1hckBueHAuY29tPjsg
VmFydW4NCj4gU2V0aGkNCj4gPiA+IDxWLlNldGhpQG54cC5jb20+DQo+ID4gPiBTdWJqZWN0OiBS
ZTogW1BBVENIIDMvNV0gZHJpdmVyczogY2xrLXFvcmlxOiBBZGQgY2xvY2tnZW4gc3VwcG9ydA0K
PiA+ID4gZm9yIGx4MjE2MGENCj4gPiA+DQo+ID4gPiBPbiBGcmksIDIwMTgtMDgtMzEgYXQgMDY6
MTIgKzAwMDAsIEFuZHkgVGFuZyB3cm90ZToNCj4gPiA+ID4gV2UgZG9uJ3Qgd2FudCB0byBpbmNy
ZWFzZSBOVU1fQ01VWCBlYWNoIHRpbWUgbmV3IHNvYyB3aXRoDQo+IG1vcmUNCj4gPiA+DQo+ID4g
PiBjbXV4ZXMgYWRkZWQuDQo+ID4gPg0KPiA+ID4gWW91IGRvbid0IHdhbnQgdG8gaGF2ZSB0byBt
YWtlIGEgdHJpdmlhbCBjaGFuZ2UgZWFjaCB0aW1lIHlvdSBleGNlZWQNCj4gPiA+IGEgbGltaXQg
dGhhdCBoYXMgeWV0IHRvIGJlIGV4Y2VlZGVkIG9uY2Ugc2luY2UgTlVNX0NNVVggd2FzIGFkZGVk
Pw0KPiA+ID4gVGhpcyBpc24ndCBBQkkgb3IgaW4gYW55IG90aGVyIHdheSBoYXJkIHRvIGNoYW5n
ZS4gIEl0J3MgcmlnaHQgaW4NCj4gPiA+IHRoZSBzYW1lIGZpbGUgYXMgdGhlIGNoaXAgZGVzY3Jp
cHRpb24geW91J2QgYmUgYWRkaW5nLg0KPiA+ID4NCj4gPiA+IEFuZCBldmVuIGlmIGEgY2hpcCBk
aWQgY29tZSBhbG9uZyB3aXRoIDE2IGNtdXhlcywgeW91J2QgdGhlbiBuZWVkIHRvDQo+ID4gPiBp
bmNyZWFzZSB0aGUgYXJyYXkgdG8gMTcgdG8gaG9sZCB0aGUgLTEgaWYgeW91IGRvbid0IHdhbnQg
dG8gbGVhdmUgYQ0KPiA+ID4gc2l0dWF0aW9uIGxpa2UgdGhlDQo+ID4gPiBwNDA4MCBpcyBpbiBu
b3csIHdoZXJlIGEgY2hpcCdzIGNtdXggYXJyYXkgY291bGQgYmUgYnJva2VuIGJ5DQo+ID4gPiBp
bmNyZWFzaW5nIE5VTV9DTVVYIGZ1cnRoZXIuDQo+ID4gPg0KPiA+DQo+ID4gW0FuZHldIEFkZGlu
ZyBidWZmZXIgdG8gYSBsaW1pdGF0aW9uIG51bWJlciBpcyBhbHdheXMgYSBnb29kIGhhYml0DQo+
ID4gd2hlbiBjb2RpbmcuIFdlIG9mdGVuIGZvcmdldCB0byBpbmNyZWFzZSB0aGlzIHZhbHVlIHdo
ZW4gYSBuZXcgY2hpcA0KPiA+IHdpdGggbW9yZSBjbXV4ZXMgYWRkZWQuDQo+IA0KPiAib2Z0ZW4i
PyAgVGhlcmUgaGFzIG5ldmVyIGJlZW4gYSBuZXcgY2hpcCBhZGRlZCB3aXRoIG1vcmUgY211eGVz
DQo+IHRoYW4gcDQwODAncyA4LCBhbmQgaWYgb25lIGRvZXMgY29tZSBhbG9uZyBhbmQgeW91IGZv
cmdldCwgdGhlIGNvbXBpbGVyDQo+IHNob3VsZCBjb21wbGFpbiBhYm91dCBleGNlZWRpbmcgdGhl
IGFycmF5IGxlbmd0aCB3aXRoIGEgc3RhdGljIGluaXRpYWxpemVyLg0KPiBUaGlzIGlzbid0IGxp
a2UgYW4gYXJyYXkgdGhhdCBpcyBmaWxsZWQgd2l0aCBhIHJ1bnRpbWUtZGV0ZXJtaW5lZCBsZW5n
dGguDQo+IA0KPiA+IExpa2UgdGhpcyBwYXRjaCwgd2UgZGlkbid0IGluY3JlYXNlIHRoaXMgdmFs
dWUgYXQgZmlyc3QuIFdlIHNwZW50IGENCj4gPiBsb3Qgb2YgdGltZSBmaW5kaW5nIG91dCB0aGF0
IE5VTV9DTVVYIG5lZWRzIHRvIGJlIGluY3JlYXNlZCB0b28uDQo+IA0KPiBBcmUgeW91IHRhbGtp
bmcgYWJvdXQgc29tZSBvdGhlciBjaGlwIHRoYXQgeW91IGhhdmVuJ3Qgc2VudCBhIHBhdGNoIGZv
cg0KPiB5ZXQ/DQo+IE9yIGlzIHRoZSBjbXV4IGFycmF5IGZvciB0aGlzIGNoaXAgd3Jvbmc/ICBX
aGF0IHNwZWNpZmljYWxseSBkaWQgeW91IHNlZQ0KPiBoYXBwZW4gImF0IGZpcnN0Ij8NCj4gDQpb
QW5keV0gU29ycnksICJPZnRlbiIgaXMgbm90IGEgcmlnaHQgd29yZC4gSSBtZWFudCB3ZSB0ZW5k
IHRvIGFkZCBuZXcgc29jIHdpdGhvdXQgdXBkYXRpbmcgTlVNX0NNVVguDQogDQo+ID4gSXQgaXMg
YSBwZXJzb25hbCBwcmVmZXJlbmNlIGhvdyB0byBzZXQgdGhpcyB2YWx1ZS4gSSB0aGluayBpdCBp
cw0KPiA+IGJldHRlciB0byBpbmNyZWFzZSBpdCB0byAxNiwgbm90IE5VTV9DTVVYKzEgYXMgbG9u
ZyBhcyB3ZSBmaXggdGhlDQo+ID4gUDQwODAgaXNzdWUgZXZlbiB0aG91Z2ggaXQgaXMgYSB0cml2
aWFsIGNoYW5nZS4gQW5kIEkgYWdyZWUgdGhlDQo+ID4gZGVzY3JpcHRpb24gbmVlZHMgdG8gYmUg
dXBkYXRlZC4NCj4gDQo+IEknbSBub3QgdGhlIGNsb2NrIG1haW50YWluZXIsIHNvIGl0J3Mgbm90
IHVwIHRvIG1lLCBidXQgSSBkb24ndCBzZWUgdGhlIHBvaW50DQo+IGluIHNldHRpbmcgaXQgdG8g
YW4gYXJiaXRyYXJ5IG51bWJlciwgYW5kIEkgZG8gbm90IGFncmVlIHRoYXQgaW5jcmVhc2luZw0K
PiBOVU1fQ01VWCBpcyBhIHN1aXRhYmxlIHJlcGxhY2VtZW50IGZvciBOVU1fQ01VWCsxIGluDQo+
IGNtdXhfdG9fZ3JvdXBbXSwgYXMgdGhhdCBhcnJheSBzaG91bGQgYmUgb25lIGxhcmdlciB0aGFu
IGNtdXhbXSBpbiBvcmRlcg0KPiB0byBhbGxvdyBldmVyeSBjaGlwIHRvIGhhdmUgYQ0KPiAtMSB0
ZXJtaW5hdG9yLiAgSW4gYW55IGNhc2UsIGFueSBjaGFuZ2UgdG8gTlVNX0NNVVggc2hvdWxkIGJl
IGENCj4gc2VwYXJhdGUgcGF0Y2ggYmVjYXVzZSBpdCdzIG5vdCByZXF1aXJlZCBmb3IgbHgyMTYw
YSBzdXBwb3J0IChhc3N1bWluZw0KPiBseDIxNjBhIHdhcyBjb3JyZWN0bHkgZGVzY3JpYmVkIGJ5
IHRoaXMgcGF0Y2gpLg0KW0FuZHldIEkgZG9uJ3Qgc2VlIGFueSBpbXByb3ByaWF0ZSBhYm91dCB5
b3VyIHN1Z2dlc3Rpb24uIHNvIHdlIGFyZSBnb2luZyB0byBkbyBpbiB5b3VyIHdheS4NCg0KVGhh
bmtzLA0KQW5keQ0KPiANCj4gLVNjb3R0DQo+IA0KPiANCj4gDQo+IF9fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fDQo+IGxpbnV4LWFybS1rZXJuZWwgbWFpbGlu
ZyBsaXN0DQo+IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZw0KPiBodHRwczov
L2VtZWEwMS5zYWZlbGlua3MucHJvdGVjdGlvbi5vdXRsb29rLmNvbS8/dXJsPWh0dHAlM0ElMkYl
MkZsaXN0DQo+IHMuaW5mcmFkZWFkLm9yZyUyRm1haWxtYW4lMkZsaXN0aW5mbyUyRmxpbnV4LWFy
bS1rZXJuZWwmYW1wO2RhdGE9MDINCj4gJTdDMDElN0NhbmR5LnRhbmclNDBueHAuY29tJTdDZGJj
ODI0ZmMzOTY3NDcxMTMxNjIwOGQ2MTFkY2YNCj4gNjFiJTdDNjg2ZWExZDNiYzJiNGM2ZmE5MmNk
OTljNWMzMDE2MzUlN0MwJTdDMCU3QzYzNjcxNjAzDQo+IDgwNjA3OTcxMTMmYW1wO3NkYXRhPWlD
TEtHTUV6UlgyZHBINSUyQmY0TldJaVBEYzVMNU5wVGNwWjdYDQo+IHVzZWhkSXclM0QmYW1wO3Jl
c2VydmVkPTANCg==
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support
2018-08-20 6:47 [PATCH 0/5] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma
` (2 preceding siblings ...)
2018-08-20 6:47 ` [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma
@ 2018-08-20 6:47 ` Vabhav Sharma
2018-08-21 10:17 ` Sudeep Holla
2018-08-20 6:47 ` [PATCH 5/5] arm64: dts: add LX2160ARDB board support Vabhav Sharma
4 siblings, 1 reply; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-20 6:47 UTC (permalink / raw)
To: linux-kernel, devicetree, robh+dt, mark.rutland, linuxppc-dev,
linux-arm-kernel, mturquette, sboyd, rjw, viresh.kumar, linux-clk,
linux-pm, linux-kernel-owner, catalin.marinas, will.deacon,
gregkh, arnd, kstewart, yamada.masahiro
Cc: linux, V.Sethi, udit.kumar, Vabhav Sharma, Ramneek Mehresh,
Zhang Ying-22455, Nipun Gupta, Priyanka Jain, Yogesh Gaur,
Sriram Dash
LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
UARTs etc.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 572 +++++++++++++++++++++++++
1 file changed, 572 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
new file mode 100644
index 0000000..e35e494
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -0,0 +1,572 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2160A family SoC.
+//
+// Copyright 2018 NXP
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,lx2160a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // 8 clusters having 2 Cortex-A72 cores each
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x1>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ clocks = <&clockgen 1 1>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ clocks = <&clockgen 1 1>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x200>;
+ clocks = <&clockgen 1 2>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x201>;
+ clocks = <&clockgen 1 2>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x300>;
+ clocks = <&clockgen 1 3>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x301>;
+ clocks = <&clockgen 1 3>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x400>;
+ clocks = <&clockgen 1 4>;
+ next-level-cache = <&cluster4_l2>;
+ };
+
+ cpu@401 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x401>;
+ clocks = <&clockgen 1 4>;
+ next-level-cache = <&cluster4_l2>;
+ };
+
+ cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x500>;
+ clocks = <&clockgen 1 5>;
+ next-level-cache = <&cluster5_l2>;
+ };
+
+ cpu@501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x501>;
+ clocks = <&clockgen 1 5>;
+ next-level-cache = <&cluster5_l2>;
+ };
+
+ cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x600>;
+ clocks = <&clockgen 1 6>;
+ next-level-cache = <&cluster6_l2>;
+ };
+
+ cpu@601 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x601>;
+ clocks = <&clockgen 1 6>;
+ next-level-cache = <&cluster6_l2>;
+ };
+
+ cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x700>;
+ clocks = <&clockgen 1 7>;
+ next-level-cache = <&cluster7_l2>;
+ };
+
+ cpu@701 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x701>;
+ clocks = <&clockgen 1 7>;
+ next-level-cache = <&cluster7_l2>;
+ };
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ };
+
+ cluster2_l2: l2-cache2 {
+ compatible = "cache";
+ };
+
+ cluster3_l2: l2-cache3 {
+ compatible = "cache";
+ };
+
+ cluster4_l2: l2-cache4 {
+ compatible = "cache";
+ };
+
+ cluster5_l2: l2-cache5 {
+ compatible = "cache";
+ };
+
+ cluster6_l2: l2-cache6 {
+ compatible = "cache";
+ };
+
+ cluster7_l2: l2-cache7 {
+ compatible = "cache";
+ };
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
+ <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
+ // SGI_base)
+ <0x0 0x0c0c0000 0 0x2000>, // GICC
+ <0x0 0x0c0d0000 0 0x1000>, // GICH
+ <0x0 0x0c0e0000 0 0x20000>; // GICV
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <1 9 0x4>;
+
+ its: gic-its@6020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0x6020000 0 0x20000>;
+ };
+ };
+
+ rstcr: syscon@1e60000 {
+ compatible = "syscon";
+ reg = <0x0 0x1e60000 0x0 0x4>;
+ };
+
+ reboot {
+ compatible ="syscon-reboot";
+ regmap = <&rstcr>;
+ offset = <0x0>;
+ mask = <0x2>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 4>, // Physical Secure PPI, active-low
+ <1 14 4>, // Physical Non-Secure PPI, active-low
+ <1 11 4>, // Virtual PPI, active-low
+ <1 10 4>; // Hypervisor PPI, active-low
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <1 7 0x8>; // PMU PPI, Level low type
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ memory@80000000 {
+ // DRAM space - 1, size : 2 GB DRAM
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ };
+
+ ddr1: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <0 17 0x4>;
+ little-endian;
+ };
+
+ ddr2: memory-controller@1090000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1090000 0x0 0x1000>;
+ interrupts = <0 18 0x4>;
+ little-endian;
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clockgen: clocking@1300000 {
+ compatible = "fsl,lx2160a-clockgen";
+ reg = <0 0x1300000 0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ dcfg: dcfg@1e00000 {
+ compatible = "fsl,lx2160a-dcfg", "syscon";
+ reg = <0x0 0x1e00000 0x0 0x10000>;
+ little-endian;
+ };
+
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ fsl-scl-gpio = <&gpio2 15 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <0 74 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ fsl-scl-gpio = <&gpio2 16 0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <0 74 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <0 75 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <0 75 0x4>; // Level high type
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ uart0: serial@21c0000 {
+ device_type = "serial";
+ compatible = "arm,pl011","arm,sbsa-uart";
+ reg = <0x0 0x21c0000 0x0 0x1000>;
+ interrupts = <0 32 0x4>; // Level high type
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart1: serial@21d0000 {
+ device_type = "serial";
+ compatible = "arm,pl011","arm,sbsa-uart";
+ reg = <0x0 0x21d0000 0x0 0x1000>;
+ interrupts = <0 33 0x4>; // Level high type
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart2: serial@21e0000 {
+ device_type = "serial";
+ compatible = "arm,pl011","arm,sbsa-uart";
+ reg = <0x0 0x21e0000 0x0 0x1000>;
+ interrupts = <0 72 0x4>; // Level high type
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart3: serial@21f0000 {
+ device_type = "serial";
+ compatible = "arm,pl011","arm,sbsa-uart";
+ reg = <0x0 0x21f0000 0x0 0x1000>;
+ interrupts = <0 73 0x4>; // Level high type
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ smmu: iommu@5000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x5000000 0 0x800000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <14>;
+ interrupts = <0 13 4>, // global secure fault
+ <0 14 4>, // combined secure interrupt
+ <0 15 4>, // global non-secure fault
+ <0 16 4>, // combined non-secure interrupt
+ // performance counter interrupts 0-9
+ <0 211 4>, <0 212 4>,
+ <0 213 4>, <0 214 4>,
+ <0 215 4>, <0 216 4>,
+ <0 217 4>, <0 218 4>,
+ <0 219 4>, <0 220 4>,
+ // per context interrupt, 64 interrupts
+ <0 146 4>, <0 147 4>,
+ <0 148 4>, <0 149 4>,
+ <0 150 4>, <0 151 4>,
+ <0 152 4>, <0 153 4>,
+ <0 154 4>, <0 155 4>,
+ <0 156 4>, <0 157 4>,
+ <0 158 4>, <0 159 4>,
+ <0 160 4>, <0 161 4>,
+ <0 162 4>, <0 163 4>,
+ <0 164 4>, <0 165 4>,
+ <0 166 4>, <0 167 4>,
+ <0 168 4>, <0 169 4>,
+ <0 170 4>, <0 171 4>,
+ <0 172 4>, <0 173 4>,
+ <0 174 4>, <0 175 4>,
+ <0 176 4>, <0 177 4>,
+ <0 178 4>, <0 179 4>,
+ <0 180 4>, <0 181 4>,
+ <0 182 4>, <0 183 4>,
+ <0 184 4>, <0 185 4>,
+ <0 186 4>, <0 187 4>,
+ <0 188 4>, <0 189 4>,
+ <0 190 4>, <0 191 4>,
+ <0 192 4>, <0 193 4>,
+ <0 194 4>, <0 195 4>,
+ <0 196 4>, <0 197 4>,
+ <0 198 4>, <0 199 4>,
+ <0 200 4>, <0 201 4>,
+ <0 202 4>, <0 203 4>,
+ <0 204 4>, <0 205 4>,
+ <0 206 4>, <0 207 4>,
+ <0 208 4>, <0 209 4>;
+ dma-coherent;
+ };
+
+ usb0: usb3@3100000 {
+ status = "disabled";
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; // Level high type
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ };
+
+ usb1: usb3@3110000 {
+ status = "disabled";
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; // Level high type
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ };
+
+ watchdog@23a0000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x23a0000 0 0x1000>,
+ <0x0 0x2390000 0 0x1000>;
+ interrupts = <0 59 4>;
+ timeout-sec = <30>;
+ };
+
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support
2018-08-20 6:47 ` [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support Vabhav Sharma
@ 2018-08-21 10:17 ` Sudeep Holla
2018-08-23 15:00 ` Vabhav Sharma
0 siblings, 1 reply; 23+ messages in thread
From: Sudeep Holla @ 2018-08-21 10:17 UTC (permalink / raw)
To: Vabhav Sharma
Cc: linux-kernel, devicetree, robh+dt, mark.rutland, linuxppc-dev,
linux-arm-kernel, mturquette, sboyd, rjw, viresh.kumar, linux-clk,
linux-pm, linux-kernel-owner, catalin.marinas, will.deacon,
gregkh, arnd, kstewart, yamada.masahiro, linux, V.Sethi,
udit.kumar, Ramneek Mehresh, Zhang Ying-22455, Nipun Gupta,
Priyanka Jain, Yogesh Gaur, Sriram Dash, Sudeep Holla
On Mon, Aug 20, 2018 at 12:17:15PM +0530, Vabhav Sharma wrote:
> LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
>
> LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
> in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
> controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
> UARTs etc.
>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 572 +++++++++++++++++++++++++
> 1 file changed, 572 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> new file mode 100644
> index 0000000..e35e494
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -0,0 +1,572 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree Include file for Layerscape-LX2160A family SoC.
> +//
> +// Copyright 2018 NXP
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x80000000 0x00010000;
> +
> +/ {
> + compatible = "fsl,lx2160a";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + // 8 clusters having 2 Cortex-A72 cores each
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0>;
> + clocks = <&clockgen 1 0>;
> + next-level-cache = <&cluster0_l2>;
If you expect to get cache properties in sysfs entries, you need to populate
them here and for each L2 cache.
[...]
> +
> + rstcr: syscon@1e60000 {
> + compatible = "syscon";
> + reg = <0x0 0x1e60000 0x0 0x4>;
> + };
> +
> + reboot {
> + compatible ="syscon-reboot";
> + regmap = <&rstcr>;
> + offset = <0x0>;
> + mask = <0x2>;
Is this disabled in bootloader ? With PSCI, it's preferred to use
SYSTEM_RESET/OFF. EL3 f/w may need to do some housekeeping on poweroff.
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <1 13 4>, // Physical Secure PPI, active-low
The comment says active low but the value 4 indicates it's HIGH from
"include/dt-bindings/interrupt-controller/irq.h"
> + <1 14 4>, // Physical Non-Secure PPI, active-low
> + <1 11 4>, // Virtual PPI, active-low
> + <1 10 4>; // Hypervisor PPI, active-low
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
More specific compatible preferably "arm,cortex-a72-pmu" ?
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support
2018-08-21 10:17 ` Sudeep Holla
@ 2018-08-23 15:00 ` Vabhav Sharma
0 siblings, 0 replies; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-23 15:00 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
linux@armlinux.org.uk, Varun Sethi, Udit Kumar, Ramneek Mehresh,
Ying Zhang, Nipun Gupta, Priyanka Jain, Yogesh Narayan Gaur,
Sriram Dash
> -----Original Message-----
> From: Sudeep Holla <sudeep.holla@arm.com>
> Sent: Tuesday, August 21, 2018 3:47 PM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org;
> linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-
> clk@vger.kernel.org; linux-pm@vger.kernel.org; linux-kernel-
> owner@vger.kernel.org; catalin.marinas@arm.com; will.deacon@arm.com;
> gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com;
> linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>; Udit Kumar
> <udit.kumar@nxp.com>; Ramneek Mehresh <ramneek.mehresh@nxp.com>;
> Ying Zhang <ying.zhang22455@nxp.com>; Nipun Gupta
> <nipun.gupta@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Yogesh
> Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Sriram Dash
> <sriram.dash@nxp.com>; Sudeep Holla <sudeep.holla@arm.com>
> Subject: Re: [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support
>=20
> On Mon, Aug 20, 2018 at 12:17:15PM +0530, Vabhav Sharma wrote:
> > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
> >
> > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor
> > cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8
> > I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011
> > SBSA UARTs etc.
> >
> > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 572
> > +++++++++++++++++++++++++
> > 1 file changed, 572 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > new file mode 100644
> > index 0000000..e35e494
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -0,0 +1,572 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree
> > +Include file for Layerscape-LX2160A family SoC.
> > +//
> > +// Copyright 2018 NXP
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/memreserve/ 0x80000000 0x00010000;
> > +
> > +/ {
> > + compatible =3D "fsl,lx2160a";
> > + interrupt-parent =3D <&gic>;
> > + #address-cells =3D <2>;
> > + #size-cells =3D <2>;
> > +
> > + cpus {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > +
> > + // 8 clusters having 2 Cortex-A72 cores each
> > + cpu@0 {
> > + device_type =3D "cpu";
> > + compatible =3D "arm,cortex-a72";
> > + reg =3D <0x0>;
> > + clocks =3D <&clockgen 1 0>;
> > + next-level-cache =3D <&cluster0_l2>;
>=20
> If you expect to get cache properties in sysfs entries, you need to popul=
ate
> them here and for each L2 cache.
Rather sysfs, If Entry is not present then print "cacheinfo: Unable to det=
ect cache hierarchy for CPU 0" appears in boot log which is bad saying some=
thing is not present.
Either this print is require change to debug instead of warning.
>=20
> [...]
>=20
> > +
> > + rstcr: syscon@1e60000 {
> > + compatible =3D "syscon";
> > + reg =3D <0x0 0x1e60000 0x0 0x4>;
> > + };
> > +
> > + reboot {
> > + compatible =3D"syscon-reboot";
> > + regmap =3D <&rstcr>;
> > + offset =3D <0x0>;
> > + mask =3D <0x2>;
>=20
> Is this disabled in bootloader ? With PSCI, it's preferred to use
> SYSTEM_RESET/OFF. EL3 f/w may need to do some housekeeping on
> poweroff.
No, PSCIv0.2 is used and control passes to EL3 fw via smc call, psci node i=
s present in the file.
This node is not required and keeping it in case PSCI is not used.
>=20
> > + };
> > +
> > + timer {
> > + compatible =3D "arm,armv8-timer";
> > + interrupts =3D <1 13 4>, // Physical Secure PPI, active-low
>=20
> The comment says active low but the value 4 indicates it's HIGH from
> "include/dt-bindings/interrupt-controller/irq.h"
Thanks, I will change the entries to existing definition IRQ_TYPE_LEVEL_LOW=
,GIC_PPI which is self-explanatory and not require comments
>=20
> > + <1 14 4>, // Physical Non-Secure PPI, active-low
> > + <1 11 4>, // Virtual PPI, active-low
> > + <1 10 4>; // Hypervisor PPI, active-low
> > + };
> > +
> > + pmu {
> > + compatible =3D "arm,armv8-pmuv3";
>=20
> More specific compatible preferably "arm,cortex-a72-pmu" ?
Sure.
>=20
> --
> Regards,
> Sudeep
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 5/5] arm64: dts: add LX2160ARDB board support
2018-08-20 6:47 [PATCH 0/5] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma
` (3 preceding siblings ...)
2018-08-20 6:47 ` [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support Vabhav Sharma
@ 2018-08-20 6:47 ` Vabhav Sharma
2018-08-21 20:45 ` Rob Herring
4 siblings, 1 reply; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-20 6:47 UTC (permalink / raw)
To: linux-kernel, devicetree, robh+dt, mark.rutland, linuxppc-dev,
linux-arm-kernel, mturquette, sboyd, rjw, viresh.kumar, linux-clk,
linux-pm, linux-kernel-owner, catalin.marinas, will.deacon,
gregkh, arnd, kstewart, yamada.masahiro
Cc: linux, V.Sethi, udit.kumar, Vabhav Sharma, Priyanka Jain,
Sriram Dash
LX2160A reference design board (RDB) is a high-performance
computing, evaluation, and development platform with LX2160A
SoC.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 95 +++++++++++++++++++++++
2 files changed, 96 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 86e18ad..445b72b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
new file mode 100644
index 0000000..70fad20
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160ARDB
+//
+// Copyright 2018 NXP
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160ARDB";
+ compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ sa56004@4c {
+ compatible = "nxp,sa56004";
+ reg = <0x4c>;
+ };
+
+ sa56004@4d {
+ compatible = "nxp,sa56004";
+ reg = <0x4d>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ // IRQ10_B
+ interrupts = <0 150 0x4>;
+ };
+
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support
2018-08-20 6:47 ` [PATCH 5/5] arm64: dts: add LX2160ARDB board support Vabhav Sharma
@ 2018-08-21 20:45 ` Rob Herring
2018-08-23 15:08 ` Vabhav Sharma
2018-08-29 0:28 ` Scott Wood
0 siblings, 2 replies; 23+ messages in thread
From: Rob Herring @ 2018-08-21 20:45 UTC (permalink / raw)
To: vabhav.sharma
Cc: linux-kernel@vger.kernel.org, devicetree, Mark Rutland,
linuxppc-dev,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Michael Turquette, Stephen Boyd, Rafael J. Wysocki, Viresh Kumar,
linux-clk, open list:THERMAL, linux-kernel-owner, Catalin Marinas,
Will Deacon, Greg Kroah-Hartman, Arnd Bergmann, Kate Stewart,
Masahiro Yamada, Russell King, V.Sethi, Udit Kumar, Priyanka Jain,
Sriram Dash
On Mon, Aug 20, 2018 at 1:52 PM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>
> LX2160A reference design board (RDB) is a high-performance
> computing, evaluation, and development platform with LX2160A
> SoC.
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 95 +++++++++++++++++++++++
> 2 files changed, 96 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 86e18ad..445b72b 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> new file mode 100644
> index 0000000..70fad20
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree file for LX2160ARDB
> +//
> +// Copyright 2018 NXP
> +
> +/dts-v1/;
> +
> +#include "fsl-lx2160a.dtsi"
> +
> +/ {
> + model = "NXP Layerscape LX2160ARDB";
> + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> +
> + aliases {
> + crypto = &crypto;
Drop this. Aliases should be numbered, and this is not a standard
alias name either.
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + };
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + pca9547@77 {
i2c-mux@77
> + compatible = "nxp,pca9547";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x2>;
> +
> + ina220@40 {
> + compatible = "ti,ina220";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> + };
> +
> + i2c@3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x3>;
> +
> + sa56004@4c {
temperature-sensor@4c
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + };
> +
> + sa56004@4d {
> + compatible = "nxp,sa56004";
> + reg = <0x4d>;
> + };
> + };
> + };
> +};
> +
> +&i2c4 {
> + status = "okay";
> +
> + rtc@51 {
> + compatible = "nxp,pcf2129";
> + reg = <0x51>;
> + // IRQ10_B
> + interrupts = <0 150 0x4>;
> + };
> +
> +};
> +
> +&usb0 {
> + status = "okay";
> +};
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> +&crypto {
> + status = "okay";
> +};
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [PATCH 5/5] arm64: dts: add LX2160ARDB board support
2018-08-21 20:45 ` Rob Herring
@ 2018-08-23 15:08 ` Vabhav Sharma
2018-08-24 16:16 ` Rob Herring
2018-08-29 0:28 ` Scott Wood
1 sibling, 1 reply; 23+ messages in thread
From: Vabhav Sharma @ 2018-08-23 15:08 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Mark Rutland, linuxppc-dev,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Michael Turquette, Stephen Boyd, Rafael J. Wysocki, Viresh Kumar,
linux-clk, open list:THERMAL, linux-kernel-owner@vger.kernel.org,
Catalin Marinas, Will Deacon, Greg Kroah-Hartman, Arnd Bergmann,
Kate Stewart, Masahiro Yamada, Russell King, Varun Sethi,
Udit Kumar, Priyanka Jain, Sriram Dash
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogUm9iIEhlcnJpbmcgPHJv
YmgrZHRAa2VybmVsLm9yZz4NCj4gU2VudDogV2VkbmVzZGF5LCBBdWd1c3QgMjIsIDIwMTggMjox
NSBBTQ0KPiBUbzogVmFiaGF2IFNoYXJtYSA8dmFiaGF2LnNoYXJtYUBueHAuY29tPg0KPiBDYzog
bGludXgta2VybmVsQHZnZXIua2VybmVsLm9yZzsgZGV2aWNldHJlZUB2Z2VyLmtlcm5lbC5vcmc7
IE1hcmsgUnV0bGFuZA0KPiA8bWFyay5ydXRsYW5kQGFybS5jb20+OyBsaW51eHBwYy1kZXYgPGxp
bnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnPjsNCj4gbW9kZXJhdGVkIGxpc3Q6QVJNL0ZSRUVT
Q0FMRSBJTVggLyBNWEMgQVJNIEFSQ0hJVEVDVFVSRSA8bGludXgtYXJtLQ0KPiBrZXJuZWxAbGlz
dHMuaW5mcmFkZWFkLm9yZz47IE1pY2hhZWwgVHVycXVldHRlIDxtdHVycXVldHRlQGJheWxpYnJl
LmNvbT47DQo+IFN0ZXBoZW4gQm95ZCA8c2JveWRAa2VybmVsLm9yZz47IFJhZmFlbCBKLiBXeXNv
Y2tpIDxyandAcmp3eXNvY2tpLm5ldD47DQo+IFZpcmVzaCBLdW1hciA8dmlyZXNoLmt1bWFyQGxp
bmFyby5vcmc+OyBsaW51eC1jbGsgPGxpbnV4LQ0KPiBjbGtAdmdlci5rZXJuZWwub3JnPjsgb3Bl
biBsaXN0OlRIRVJNQUwgPGxpbnV4LXBtQHZnZXIua2VybmVsLm9yZz47IGxpbnV4LQ0KPiBrZXJu
ZWwtb3duZXJAdmdlci5rZXJuZWwub3JnOyBDYXRhbGluIE1hcmluYXMgPGNhdGFsaW4ubWFyaW5h
c0Bhcm0uY29tPjsNCj4gV2lsbCBEZWFjb24gPHdpbGwuZGVhY29uQGFybS5jb20+OyBHcmVnIEty
b2FoLUhhcnRtYW4NCj4gPGdyZWdraEBsaW51eGZvdW5kYXRpb24ub3JnPjsgQXJuZCBCZXJnbWFu
biA8YXJuZEBhcm5kYi5kZT47IEthdGUNCj4gU3Rld2FydCA8a3N0ZXdhcnRAbGludXhmb3VuZGF0
aW9uLm9yZz47IE1hc2FoaXJvIFlhbWFkYQ0KPiA8eWFtYWRhLm1hc2FoaXJvQHNvY2lvbmV4dC5j
b20+OyBSdXNzZWxsIEtpbmcgPGxpbnV4QGFybWxpbnV4Lm9yZy51az47DQo+IFZhcnVuIFNldGhp
IDxWLlNldGhpQG54cC5jb20+OyBVZGl0IEt1bWFyIDx1ZGl0Lmt1bWFyQG54cC5jb20+Ow0KPiBQ
cml5YW5rYSBKYWluIDxwcml5YW5rYS5qYWluQG54cC5jb20+OyBTcmlyYW0gRGFzaA0KPiA8c3Jp
cmFtLmRhc2hAbnhwLmNvbT4NCj4gU3ViamVjdDogUmU6IFtQQVRDSCA1LzVdIGFybTY0OiBkdHM6
IGFkZCBMWDIxNjBBUkRCIGJvYXJkIHN1cHBvcnQNCj4gDQo+IE9uIE1vbiwgQXVnIDIwLCAyMDE4
IGF0IDE6NTIgUE0gVmFiaGF2IFNoYXJtYQ0KPiA8dmFiaGF2LnNoYXJtYUBueHAuY29tPiB3cm90
ZToNCj4gPg0KPiA+IExYMjE2MEEgcmVmZXJlbmNlIGRlc2lnbiBib2FyZCAoUkRCKSBpcyBhIGhp
Z2gtcGVyZm9ybWFuY2UgY29tcHV0aW5nLA0KPiA+IGV2YWx1YXRpb24sIGFuZCBkZXZlbG9wbWVu
dCBwbGF0Zm9ybSB3aXRoIExYMjE2MEEgU29DLg0KPiA+DQo+ID4gU2lnbmVkLW9mZi1ieTogUHJp
eWFua2EgSmFpbiA8cHJpeWFua2EuamFpbkBueHAuY29tPg0KPiA+IFNpZ25lZC1vZmYtYnk6IFNy
aXJhbSBEYXNoIDxzcmlyYW0uZGFzaEBueHAuY29tPg0KPiA+IFNpZ25lZC1vZmYtYnk6IFZhYmhh
diBTaGFybWEgPHZhYmhhdi5zaGFybWFAbnhwLmNvbT4NCj4gPiAtLS0NCj4gPiAgYXJjaC9hcm02
NC9ib290L2R0cy9mcmVlc2NhbGUvTWFrZWZpbGUgICAgICAgICAgICB8ICAxICsNCj4gPiAgYXJj
aC9hcm02NC9ib290L2R0cy9mcmVlc2NhbGUvZnNsLWx4MjE2MGEtcmRiLmR0cyB8IDk1DQo+ID4g
KysrKysrKysrKysrKysrKysrKysrKysNCj4gPiAgMiBmaWxlcyBjaGFuZ2VkLCA5NiBpbnNlcnRp
b25zKCspDQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybTY0L2Jvb3QvZHRzL2ZyZWVz
Y2FsZS9mc2wtbHgyMTYwYS1yZGIuZHRzDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02
NC9ib290L2R0cy9mcmVlc2NhbGUvTWFrZWZpbGUNCj4gPiBiL2FyY2gvYXJtNjQvYm9vdC9kdHMv
ZnJlZXNjYWxlL01ha2VmaWxlDQo+ID4gaW5kZXggODZlMThhZC4uNDQ1YjcyYiAxMDA2NDQNCj4g
PiAtLS0gYS9hcmNoL2FybTY0L2Jvb3QvZHRzL2ZyZWVzY2FsZS9NYWtlZmlsZQ0KPiA+ICsrKyBi
L2FyY2gvYXJtNjQvYm9vdC9kdHMvZnJlZXNjYWxlL01ha2VmaWxlDQo+ID4gQEAgLTEzLDMgKzEz
LDQgQEAgZHRiLSQoQ09ORklHX0FSQ0hfTEFZRVJTQ0FQRSkgKz0gZnNsLWxzMjA4MGEtDQo+IHJk
Yi5kdGINCj4gPiAgZHRiLSQoQ09ORklHX0FSQ0hfTEFZRVJTQ0FQRSkgKz0gZnNsLWxzMjA4MGEt
c2ltdS5kdGINCj4gPiAgZHRiLSQoQ09ORklHX0FSQ0hfTEFZRVJTQ0FQRSkgKz0gZnNsLWxzMjA4
OGEtcWRzLmR0Yg0KPiA+ICBkdGItJChDT05GSUdfQVJDSF9MQVlFUlNDQVBFKSArPSBmc2wtbHMy
MDg4YS1yZGIuZHRiDQo+ID4gK2R0Yi0kKENPTkZJR19BUkNIX0xBWUVSU0NBUEUpICs9IGZzbC1s
eDIxNjBhLXJkYi5kdGINCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9ib290L2R0cy9mcmVl
c2NhbGUvZnNsLWx4MjE2MGEtcmRiLmR0cw0KPiA+IGIvYXJjaC9hcm02NC9ib290L2R0cy9mcmVl
c2NhbGUvZnNsLWx4MjE2MGEtcmRiLmR0cw0KPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4g
aW5kZXggMDAwMDAwMC4uNzBmYWQyMA0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9hcmNo
L2FybTY0L2Jvb3QvZHRzL2ZyZWVzY2FsZS9mc2wtbHgyMTYwYS1yZGIuZHRzDQo+ID4gQEAgLTAs
MCArMSw5NSBAQA0KPiA+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogKEdQTC0yLjAgT1Ig
TUlUKSAvLyAvLyBEZXZpY2UgVHJlZSBmaWxlDQo+ID4gK2ZvciBMWDIxNjBBUkRCIC8vIC8vIENv
cHlyaWdodCAyMDE4IE5YUA0KPiA+ICsNCj4gPiArL2R0cy12MS87DQo+ID4gKw0KPiA+ICsjaW5j
bHVkZSAiZnNsLWx4MjE2MGEuZHRzaSINCj4gPiArDQo+ID4gKy8gew0KPiA+ICsgICAgICAgbW9k
ZWwgPSAiTlhQIExheWVyc2NhcGUgTFgyMTYwQVJEQiI7DQo+ID4gKyAgICAgICBjb21wYXRpYmxl
ID0gImZzbCxseDIxNjBhLXJkYiIsICJmc2wsbHgyMTYwYSI7DQo+ID4gKw0KPiA+ICsgICAgICAg
YWxpYXNlcyB7DQo+ID4gKyAgICAgICAgICAgICAgIGNyeXB0byA9ICZjcnlwdG87DQo+IA0KPiBE
cm9wIHRoaXMuIEFsaWFzZXMgc2hvdWxkIGJlIG51bWJlcmVkLCBhbmQgdGhpcyBpcyBub3QgYSBz
dGFuZGFyZCBhbGlhcyBuYW1lDQo+IGVpdGhlci4NCk9rDQo+IA0KPiA+ICsgICAgICAgICAgICAg
ICBzZXJpYWwwID0gJnVhcnQwOw0KPiA+ICsgICAgICAgICAgICAgICBzZXJpYWwxID0gJnVhcnQx
Ow0KPiA+ICsgICAgICAgICAgICAgICBzZXJpYWwyID0gJnVhcnQyOw0KPiA+ICsgICAgICAgICAg
ICAgICBzZXJpYWwzID0gJnVhcnQzOw0KPiA+ICsgICAgICAgfTsNCj4gPiArICAgICAgIGNob3Nl
biB7DQo+ID4gKyAgICAgICAgICAgICAgIHN0ZG91dC1wYXRoID0gInNlcmlhbDA6MTE1MjAwbjgi
Ow0KPiA+ICsgICAgICAgfTsNCj4gPiArfTsNCj4gPiArDQo+ID4gKyZ1YXJ0MCB7DQo+ID4gKyAg
ICAgICBzdGF0dXMgPSAib2theSI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsmdWFydDEgew0KPiA+
ICsgICAgICAgc3RhdHVzID0gIm9rYXkiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArJmkyYzAgew0K
PiA+ICsgICAgICAgc3RhdHVzID0gIm9rYXkiOw0KPiA+ICsgICAgICAgcGNhOTU0N0A3NyB7DQo+
IA0KPiBpMmMtbXV4QDc3DQpTdXJlDQo+IA0KPiA+ICsgICAgICAgICAgICAgICBjb21wYXRpYmxl
ID0gIm54cCxwY2E5NTQ3IjsNCj4gPiArICAgICAgICAgICAgICAgcmVnID0gPDB4Nzc+Ow0KPiA+
ICsgICAgICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwxPjsNCj4gPiArICAgICAgICAgICAg
ICAgI3NpemUtY2VsbHMgPSA8MD47DQo+ID4gKw0KPiA+ICsgICAgICAgICAgICAgICBpMmNAMiB7
DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgI2FkZHJlc3MtY2VsbHMgPSA8MT47DQo+ID4g
KyAgICAgICAgICAgICAgICAgICAgICAgI3NpemUtY2VsbHMgPSA8MD47DQo+ID4gKyAgICAgICAg
ICAgICAgICAgICAgICAgcmVnID0gPDB4Mj47DQo+ID4gKw0KPiA+ICsgICAgICAgICAgICAgICAg
ICAgICAgIGluYTIyMEA0MCB7DQpwb3dlci1zZW5zb3JANDANCj4gPiArICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAidGksaW5hMjIwIjsNCj4gPiArICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgIHJlZyA9IDwweDQwPjsNCj4gPiArICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgIHNodW50LXJlc2lzdG9yID0gPDEwMDA+Ow0KPiA+ICsgICAgICAgICAg
ICAgICAgICAgICAgIH07DQo+ID4gKyAgICAgICAgICAgICAgIH07DQo+ID4gKw0KPiA+ICsgICAg
ICAgICAgICAgICBpMmNAMyB7DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgI2FkZHJlc3Mt
Y2VsbHMgPSA8MT47DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgI3NpemUtY2VsbHMgPSA8
MD47DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgcmVnID0gPDB4Mz47DQo+ID4gKw0KPiA+
ICsgICAgICAgICAgICAgICAgICAgICAgIHNhNTYwMDRANGMgew0KPiANCj4gdGVtcGVyYXR1cmUt
c2Vuc29yQDRjDQpPaywgdGVtcGVyYXR1cmUtc2Vuc29yLTFANGMNCj4gDQo+ID4gKyAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICBjb21wYXRpYmxlID0gIm54cCxzYTU2MDA0IjsNCj4gPiAr
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJlZyA9IDwweDRjPjsNCj4gPiArICAgICAg
ICAgICAgICAgICAgICAgICB9Ow0KPiA+ICsNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBz
YTU2MDA0QDRkIHsNCk9rLHRlbXBlcmF0dXJlLXNlbnNvci0yQDRkDQo+ID4gKyAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICBjb21wYXRpYmxlID0gIm54cCxzYTU2MDA0IjsNCj4gPiArICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJlZyA9IDwweDRkPjsNCj4gPiArICAgICAgICAg
ICAgICAgICAgICAgICB9Ow0KPiA+ICsgICAgICAgICAgICAgICB9Ow0KPiA+ICsgICAgICAgfTsN
Cj4gPiArfTsNCj4gPiArDQo+ID4gKyZpMmM0IHsNCj4gPiArICAgICAgIHN0YXR1cyA9ICJva2F5
IjsNCj4gPiArDQo+ID4gKyAgICAgICBydGNANTEgew0KPiA+ICsgICAgICAgICAgICAgICBjb21w
YXRpYmxlID0gIm54cCxwY2YyMTI5IjsNCj4gPiArICAgICAgICAgICAgICAgcmVnID0gPDB4NTE+
Ow0KPiA+ICsgICAgICAgICAgICAgICAvLyBJUlExMF9CDQo+ID4gKyAgICAgICAgICAgICAgIGlu
dGVycnVwdHMgPSA8MCAxNTAgMHg0PjsNCj4gPiArICAgICAgICAgICAgICAgfTsNCj4gPiArDQo+
ID4gK307DQo+ID4gKw0KPiA+ICsmdXNiMCB7DQo+ID4gKyAgICAgICBzdGF0dXMgPSAib2theSI7
DQo+ID4gK307DQo+ID4gKw0KPiA+ICsmdXNiMSB7DQo+ID4gKyAgICAgICBzdGF0dXMgPSAib2th
eSI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsmY3J5cHRvIHsNCj4gPiArICAgICAgIHN0YXR1cyA9
ICJva2F5IjsNCj4gPiArfTsNCj4gPiAtLQ0KPiA+IDIuNy40DQo+ID4NCg==
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support
2018-08-23 15:08 ` Vabhav Sharma
@ 2018-08-24 16:16 ` Rob Herring
0 siblings, 0 replies; 23+ messages in thread
From: Rob Herring @ 2018-08-24 16:16 UTC (permalink / raw)
To: vabhav.sharma
Cc: linux-kernel@vger.kernel.org, devicetree, Mark Rutland,
linuxppc-dev,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Michael Turquette, Stephen Boyd, Rafael J. Wysocki, Viresh Kumar,
linux-clk, open list:THERMAL, linux-kernel-owner, Catalin Marinas,
Will Deacon, Greg Kroah-Hartman, Arnd Bergmann, Kate Stewart,
Masahiro Yamada, Russell King, V.Sethi, Udit Kumar, Priyanka Jain,
Sriram Dash
On Thu, Aug 23, 2018 at 10:08 AM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
[...]
> > > + i2c@3 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + reg = <0x3>;
> > > +
> > > + sa56004@4c {
> >
> > temperature-sensor@4c
> Ok, temperature-sensor-1@4c
No, that's not what I said. You don't need the '-1' because the
unit-address makes the node name unique. Node names are supposed to be
generic based on the class/type of device. See the DT spec.
> >
> > > + compatible = "nxp,sa56004";
> > > + reg = <0x4c>;
> > > + };
> > > +
> > > + sa56004@4d {
> Ok,temperature-sensor-2@4d
> > > + compatible = "nxp,sa56004";
> > > + reg = <0x4d>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&i2c4 {
> > > + status = "okay";
> > > +
> > > + rtc@51 {
> > > + compatible = "nxp,pcf2129";
> > > + reg = <0x51>;
> > > + // IRQ10_B
> > > + interrupts = <0 150 0x4>;
> > > + };
> > > +
> > > +};
> > > +
> > > +&usb0 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&usb1 {
> > > + status = "okay";
> > > +};
> > > +
> > > +&crypto {
> > > + status = "okay";
> > > +};
> > > --
> > > 2.7.4
> > >
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support
2018-08-21 20:45 ` Rob Herring
2018-08-23 15:08 ` Vabhav Sharma
@ 2018-08-29 0:28 ` Scott Wood
2018-10-11 10:04 ` Horia Geanta
1 sibling, 1 reply; 23+ messages in thread
From: Scott Wood @ 2018-08-29 0:28 UTC (permalink / raw)
To: Rob Herring, vabhav.sharma
Cc: Mark Rutland, Kate Stewart, linux-kernel-owner, Viresh Kumar,
Michael Turquette, Will Deacon, Masahiro Yamada, Sriram Dash,
linux-clk, Udit Kumar, Russell King, Catalin Marinas, devicetree,
Arnd Bergmann, open list:THERMAL, V.Sethi,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Stephen Boyd, Priyanka Jain, Rafael J. Wysocki,
linux-kernel@vger.kernel.org, Greg Kroah-Hartman, linuxppc-dev
On Tue, 2018-08-21 at 15:45 -0500, Rob Herring wrote:
> On Mon, Aug 20, 2018 at 1:52 PM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
> > +/ {
> > + model = "NXP Layerscape LX2160ARDB";
> > + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> > +
> > + aliases {
> > + crypto = &crypto;
>
> Drop this. Aliases should be numbered, and this is not a standard
> alias name either.
Is this a new rule? In any case, U-Boot looks for a "crypto" alias.
-Scott
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support
2018-08-29 0:28 ` Scott Wood
@ 2018-10-11 10:04 ` Horia Geanta
0 siblings, 0 replies; 23+ messages in thread
From: Horia Geanta @ 2018-10-11 10:04 UTC (permalink / raw)
To: Scott Wood, Rob Herring, Vabhav Sharma
Cc: Mark Rutland, Kate Stewart, devicetree@vger.kernel.org,
Viresh Kumar, Michael Turquette, Will Deacon, Masahiro Yamada,
Sriram Dash, linux-clk, Udit Kumar, Russell King, Catalin Marinas,
linux-kernel-owner@vger.kernel.org, Arnd Bergmann,
open list:THERMAL, Varun Sethi,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Stephen Boyd, Priyanka Jain, Rafael J. Wysocki,
linux-kernel@vger.kernel.org, Greg Kroah-Hartman, linuxppc-dev
On 8/29/2018 3:31 AM, Scott Wood wrote:
> On Tue, 2018-08-21 at 15:45 -0500, Rob Herring wrote:
>> On Mon, Aug 20, 2018 at 1:52 PM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>>> +/ {
>>> + model = "NXP Layerscape LX2160ARDB";
>>> + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
>>> +
>>> + aliases {
>>> + crypto = &crypto;
>>
>> Drop this. Aliases should be numbered, and this is not a standard
>> alias name either.
>
> Is this a new rule? In any case, U-Boot looks for a "crypto" alias.
>
(Replying here, I did not see a follow-up).
Indeed, U-boot relies on the "crypto" alias.
This is true for all SoCs with CAAM crypto engine, a pretty lengthy list.
Could you please clarify?
Also: Is numbering needed even when there is a single instance of the block?
Looking at a recent discussion
https://lore.kernel.org/patchwork/patch/991718
I see the proposal is for the ID to be optional:
> Alias names are often suffixed with a numeric ID, especially when there may
> be multiple instances of the same type. The ID typically corresponds to the
[...]
Thanks,
Horia
^ permalink raw reply [flat|nested] 23+ messages in thread