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Subject: Re: [RFC Part1 PATCH v3 15/17] x86: Add support for changing memory
 encryption attribute in early boot
To: Borislav Petkov <bp@suse.de>, Tom Lendacky <thomas.lendacky@amd.com>
References: <20170724190757.11278-1-brijesh.singh@amd.com>
 <20170724190757.11278-16-brijesh.singh@amd.com>
 <20170828105119.xs73tinknqcmrgvk@pd.tnic>
From: Brijesh Singh <brijesh.singh@amd.com>
Message-ID: <4b3cec09-ab6a-0400-00fe-328b36564942@amd.com>
Date: Mon, 28 Aug 2017 06:49:19 -0500
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Hi Boris,


On 8/28/17 5:51 AM, Borislav Petkov wrote:

[..]

> +static int __init early_set_memory_enc_dec(resource_size_t paddr,
>> +					   unsigned long size, bool enc)
>> +{
>> +	unsigned long vaddr, vaddr_end, vaddr_next;
>> +	unsigned long psize, pmask;
>> +	int split_page_size_mask;
>> +	pte_t *kpte;
>> +	int level;
>> +
>> +	vaddr = (unsigned long)__va(paddr);
>> +	vaddr_next = vaddr;
>> +	vaddr_end = vaddr + size;
>> +
>> +	/*
>> +	 * We are going to change the physical page attribute from C=1 to C=0
>> +	 * or vice versa. Flush the caches to ensure that data is written into
>> +	 * memory with correct C-bit before we change attribute.
>> +	 */
>> +	clflush_cache_range(__va(paddr), size);
>> +
>> +	for (; vaddr < vaddr_end; vaddr = vaddr_next) {
>> +		kpte = lookup_address(vaddr, &level);
>> +		if (!kpte || pte_none(*kpte))
>> +			return 1;
> Return before flushing TLBs? Perhaps you mean
>
> 			ret = 1;
> 			goto out;
>
> here and out does
>
> 	__flush_tlb_all();
> 	return ret;

thanks, good catch. I will fix in next rev.

-Brijesh