From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from nf-out-0910.google.com (nf-out-0910.google.com [64.233.182.190]) by ozlabs.org (Postfix) with ESMTP id 9720DDDEF4 for ; Wed, 20 Dec 2006 04:34:18 +1100 (EST) Received: by nf-out-0910.google.com with SMTP id n15so2020021nfc for ; Tue, 19 Dec 2006 09:34:16 -0800 (PST) Message-ID: <4b73d43f0612190934t53fdd35ap98243ba107eb446c@mail.gmail.com> Date: Tue, 19 Dec 2006 10:34:16 -0700 From: "John Rigby" To: "Pedro Luis D. L." Subject: Re: LITE5200B Powerfail In-Reply-To: <4b73d43f0612151752x1602392ehe9933e71fa1ac456@mail.gmail.com> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_12331_22589006.1166549656169" References: <4b73d43f0612151752x1602392ehe9933e71fa1ac456@mail.gmail.com> Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------=_Part_12331_22589006.1166549656169 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Content-Disposition: inline According to the Lite5200B schematic http://www.freescale.com/files/32bit/hardware_tools/schematics/lite5200BSCH= .pdf PSC2_4 is tied to a signal called PWR_DN_CTL_STS via a zero ohm resistor R88. If you want to use PSC2_4 as something else you probably need to remove R88. On 12/15/06, John Rigby wrote: > > Have you looked at the Lite5200B schematic to see where the signals in > question go? Maybe you trying to drive something tied to ground high or > vice-versa. > > On 12/15/06, Pedro Luis D. L. wrote: > > > > Hi all, > > > > I not pretty sure if this is the correct forum to ask for a solution bu= t > > I > > know that some of you have worked on a driver to make PSCs in this boar= d > > work in an I2S mode. > > > > Have you ever have powerfail problems when writing the configuration > > registers for this mode? > > > > I=B4ve delimited the problem: > > - GPIO Port Config register stores without problems the value "111" in > > bits > > 25:27 (PSC2 to work in CODEC2 functionality with MCLK). > > - When I write a "1" in PSC2->SICR register bit GenClk to ensure that > > clock > > and FrameSync are generated internally from MCLK the systems suffers a > > powerfail and I suppose that=B4s consecuence or some kind of shortcircu= it. > > I=B4ve followed the same steps made by Bob Peterson in > > http://ozlabs.org/pipermail/linuxppc-embedded/2005-September/020210.htm= l > > to write the configuration in the proper registers but I still suffer > > the > > powerfail when GenClk is activated or, if I activate that bit first, > > when > > Port Config is written. > > I=B4m also trying to understand how things are done in Roman Fietze dri= ver > > but > > can=B4t find a difference. That makes me think that perhaps other > > registers > > must be modificated before driver loading. Meanwhile, I keep waiting fo= r > > > > Grant Likely release, :-). > > Has this happened to someone before? > > > > Thanks for your help. > > > > Pedro. > > > > _________________________________________________________________ > > Hor=F3scopo, tarot, numerolog=EDa... Escucha lo que te dicen los astros= . > > http://astrocentro.msn.es/ > > > > _______________________________________________ > > Linuxppc-embedded mailing list > > Linuxppc-embedded@ozlabs.org > > https://ozlabs.org/mailman/listinfo/linuxppc-embedded > > > > ------=_Part_12331_22589006.1166549656169 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline According to the Lite5200B schematic http://www.freescale.= com/files/32bit/hardware_tools/schematics/lite5200BSCH.pdf

PSC2_= 4 is tied to a signal called PWR_DN_CTL_STS via a zero ohm resistor R88.&nb= sp; If you want to use PSC2_4 as something else you probably need to remove= R88.

On 12/15/06, John Rigby <jcrigby@gm= ail.com> wrote:
Have you looked at the Lite5200B schematic to see where t= he signals in question go?  Maybe you trying to drive something tied to ground high or vice-versa.

On 12/15/06, Pedro Luis D. L. < carcadiz@hotmail.com> wrote:
Hi all,

I not pretty sure if this is the correct forum to ask for a = solution but I
know that some of you have worked on a driver to make PSC= s in this board
work in an I2S mode.

Have you ever have powerfail= problems when writing the configuration
registers for this mode?

I=B4ve delimited the problem:
- GPIO= Port Config register stores without problems the value "111" in = bits
25:27 (PSC2 to work in CODEC2 functionality with MCLK).
- When I= write a "1" in PSC2->SICR register bit GenClk  to e= nsure that clock
and FrameSync are generated internally from MCLK the systems suffers a<= br>powerfail and I suppose that=B4s consecuence or some kind of shortcircui= t.
I=B4ve followed the same steps made by Bob Peterson in
http://ozlabs.org/pipermail/linuxppc-embedded/2005-September/020210.html
to write the configuration in the proper registers but I still suffer = the
powerfail when GenClk is activated or, if I activate that bit first,= when
Port Config is written.
I=B4m also trying to understand how things a= re done in Roman Fietze driver but
can=B4t find a difference. That makes= me think that perhaps other registers
must be modificated before driver= loading. Meanwhile, I keep waiting for
Grant Likely release, :-).
Has this happened to someone before?
<= br>Thanks for your help.

    Pedro.

_____= ____________________________________________________________
Hor=F3scopo= , tarot, numerolog=EDa... Escucha lo que te dicen los astros.
http://astrocentro.msn.es/
_______________________________________________
Linuxppc-embedded = mailing list
Linuxppc-embedded@ozlab= s.org
h= ttps://ozlabs.org/mailman/listinfo/linuxppc-embedded


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