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Wed, 2 Nov 2022 23:02:37 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D82215204E; Wed, 2 Nov 2022 23:02:37 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 8297A52050; Wed, 2 Nov 2022 23:02:37 +0000 (GMT) Received: from li-0d7fa1cc-2c9d-11b2-a85c-aed20764436d.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 8B0C66010C; Thu, 3 Nov 2022 10:02:34 +1100 (AEDT) Message-ID: <4e1de0ca6885ff297a19a0ef17fc4446a4231f75.camel@linux.ibm.com> Subject: Re: [PATCH v9 4/7] powerpc/code-patching: Verify instruction patch succeeded From: Benjamin Gray To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org Date: Thu, 03 Nov 2022 10:02:34 +1100 In-Reply-To: <20a4382b-089a-442a-ad05-af893823c9dc@csgroup.eu> References: <20221025044409.448755-1-bgray@linux.ibm.com> <20221025044409.448755-5-bgray@linux.ibm.com> <83e63455-95d8-88bf-82b2-c72bfe288fab@csgroup.eu> <20a4382b-089a-442a-ad05-af893823c9dc@csgroup.eu> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4 (3.44.4-2.fc36) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: DlwcBDMDYOo8U5jIP21xC_fE0smoDcqA X-Proofpoint-GUID: 6Dle5aw0xunOXk58Q12S0xYkg7TXLXX5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-02_15,2022-11-02_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 phishscore=0 impostorscore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 priorityscore=1501 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211020154 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jniethe5@gmail.com, cmr@bluescreens.de, ajd@linux.ibm.com, npiggin@gmail.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, 2022-11-02 at 11:13 +0100, Christophe Leroy wrote: > Le 02/11/2022 =C3=A0 10:43, Christophe Leroy a =C3=A9crit=C2=A0: > > Le 25/10/2022 =C3=A0 06:44, Benjamin Gray a =C3=A9crit=C2=A0: > > > Verifies that if the instruction patching did not return an error > > > then > > > the value stored at the given address to patch is now equal to > > > the > > > instruction we patched it to. > >=20 > > Why do we need that verification ? Until now it wasn't necessary, > > can=20 > > you describe a failure that occurs because we don't have this=20 > > verification ? Or is that until now it was reliable but the new > > method=20 > > you are adding will not be as reliable as before ? > >=20 > > What worries me with that new verification is that you are reading > > a=20 > > memory address with is mostly only used for code execution. That > > means: > > - You will almost always take a DATA TLB Miss, hence performance > > impact. > > - If one day we want Exec-only text mappings, it will become > > problematic. > >=20 > > So really the question is, is that patch really required ? > >=20 > > >=20 > > > Signed-off-by: Benjamin Gray > > > --- > > > =C2=A0 arch/powerpc/lib/code-patching.c | 2 ++ > > > =C2=A0 1 file changed, 2 insertions(+) > > >=20 > > > diff --git a/arch/powerpc/lib/code-patching.c=20 > > > b/arch/powerpc/lib/code-patching.c > > > index 3b3b09d5d2e1..b0a12b2d5a9b 100644 > > > --- a/arch/powerpc/lib/code-patching.c > > > +++ b/arch/powerpc/lib/code-patching.c > > > @@ -192,6 +192,8 @@ static int do_patch_instruction(u32 *addr,=20 > > > ppc_inst_t instr) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 err =3D __do_patch_instruction(addr, i= nstr); > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 local_irq_restore(flags); > > > +=C2=A0=C2=A0=C2=A0 WARN_ON(!err && !ppc_inst_equal(instr, > > > ppc_inst_read(addr))); > > > + >=20 > Another point: you are doing the check outside of IRQ disabled > section,=20 > is that correct ? What if an interrupt changed it in-between ? >=20 > Or insn't that possible ? In that case what's the real purpose of=20 > disabling IRQs here ? Disabling IRQ's also serves to prevent the writeable mapping being visible outside of the patching function from my understanding. But I would move the check inside the disabled section if I were keeping it.