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Date: Fri, 3 Aug 2012 11:44:55 -0500
From: Scott Wood <scottwood@freescale.com>
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To: Kumar Gala <galak@kernel.crashing.org>
Subject: Re: [PATCH 3/3 v3] powerpc/mpic: FSL MPIC error interrupt support.
References: <1343745764-3788-1-git-send-email-Varun.Sethi@freescale.com>
 <609EA81E-EC64-4539-B36B-E57525CE2492@kernel.crashing.org>
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Cc: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>,
 Varun Sethi <Varun.Sethi@freescale.com>, linuxppc-dev@lists.ozlabs.org
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On 08/03/2012 08:19 AM, Kumar Gala wrote:
> 
> On Jul 31, 2012, at 9:42 AM, Varun Sethi wrote:
>> +	/* ioremap'ed base for error interrupt registers */
>> +	u32 __iomem	*err_regs;
>> +	/* error interrupt config */
>> +	u32			err_int_config_done;
>> +
> 
> Is this really needed ?

Probably a left over from when it was done on demand.

> 
>> 	/* Protected sources */
>> 	unsigned long		*protected;
>>
>> @@ -370,6 +381,8 @@ struct mpic
>> #define MPIC_NO_RESET			0x00004000
>> /* Freescale MPIC (compatible includes "fsl,mpic") */
>> #define MPIC_FSL			0x00008000
>> +/* Freescale MPIC supports EIMR (error interrupt mask register)*/
>> +#define MPIC_FSL_HAS_EIMR		0x00010000
> 
> Can't we use BRR for this?

BRR is used, and this is set as a result.  Better than opencoding a BRR
check a bunch of places...

-Scott