On Tue, 2013-01-15 at 15:38 +0800, Mike Qiu wrote:
Currently, multiple MSI feature hasn't been enabled in pSeries,
These patches try to enbale this feature.
Hi Mike,
These patches have been tested by using ipr driver, and the driver patch
has been made by Wen Xiong <wenxiong@linux.vnet.ibm.com>:
So who wrote these patches? Normally we would expect the original author
to post the patches if at all possible.
Hi Michael
Test platform: One partition of pSeries with one cpu core(4 SMTs) and
RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7
OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel
IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI.
The test results is shown by 'cat /proc/interrups':
CPU0 CPU1 CPU2 CPU3
21: 6 5 5 5 XICS Level host1-0
22: 817 814 816 813 XICS Level host1-1
This shows that you are correctly configuring two MSIs.
But the key advantage of using multiple interrupts is to distribute load
across CPUs and improve performance. So I would like to see some
performance numbers that show that there is a real benefit for all the
extra complexity in the code.
Yes, the system just has suport two MSIs. Anyway, I will try to do
some proformance