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Date: Fri, 07 Jun 2013 07:09:43 -0500
From: Timur Tabi <timur@tabi.org>
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To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: SATA FSL and upstreaming
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Cc: Xie Shaohui-B21989 <B21989@freescale.com>,
 Liu Qiang-B32616 <B32616@freescale.com>,
 Zang Roy-R61911 <r61911@freescale.com>,
 "tiejun.chen" <tiejun.chen@windriver.com>,
 Fleming Andy-AFLEMING <afleming@freescale.com>,
 Bhushan Bharat-R65777 <R65777@freescale.com>,
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Benjamin Herrenschmidt wrote:
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out

This usually means that your RCW does not match your dip switch settings.

-- 
Timur Tabi