From: York Sun <yorksun@freescale.com>
To: Scott Wood <scottwood@freescale.com>
Cc: albrecht.dress@arcor.de, linuxppc-dev@lists.ozlabs.org
Subject: Re: [RFC] power/mpc85xx: Add delay after enabling I2C master
Date: Tue, 23 Jul 2013 13:32:51 -0700 [thread overview]
Message-ID: <51EEE873.8090002@freescale.com> (raw)
In-Reply-To: <1374604984.15592.34@snotra>
On 07/23/2013 11:43 AM, Scott Wood wrote:
>>
>> Yes. The max divider from sys clock to i2c clcok is 32K.
>> i2c->real_clk is the clock I2C controller pumps out, not its internal
>> operation clock.
>
> 32K is the max for all implementations?
Yes, according to application note 2919 (published).
>
> BTW, Where does the "2000000" come from? Shouldn't it be 1000000 if
> you're converting to usec? If you're trying to add some slack, say so
> rather than having a comment suggest that the output of that formula is
> 64K cycles. Or is there an implicit assumption that i2c runs at half
> the system frequency? Is that assumption true for all implementations
> that have this erratum?
The clock source is half the sysclk. This erratum applies to selected
85xx SoCs. I have confirmed with application team that it is safe to
apply the delay to all 85xx.
>
>> > In any case, you should send this patch to the i2c maintainer and list.
>> >
>>
>> I don't have the name on top of my head. Is that
>> linux-i2c@vger.kernel.org?
>
> Yes, and Wolfram Sang <wsa@the-dreams.de> is the maintainer. This is
> listed in the MAINTAINERS file.
>
I can resubmit this patch after the feedback is addressed.
York
prev parent reply other threads:[~2013-07-23 20:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-13 21:27 [PATCH RFC] power/mpc85xx: Add delay after enabling I2C master York Sun
2013-07-23 0:33 ` [RFC] " Scott Wood
2013-07-23 15:37 ` York Sun
2013-07-23 18:43 ` Scott Wood
2013-07-23 20:32 ` York Sun [this message]
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