From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from fmmailgate05.web.de (fmmailgate05.web.de [217.72.192.243]) by ozlabs.org (Postfix) with ESMTP id C550DDDF3C for ; Thu, 10 Jan 2008 21:14:50 +1100 (EST) Received: from web.de by fmmailgate05.web.de (Postfix) with SMTP id AC70A3B32219 for ; Thu, 10 Jan 2008 11:13:19 +0100 (CET) Date: Thu, 10 Jan 2008 11:13:19 +0100 Message-Id: <525760687@web.de> MIME-Version: 1.0 From: Joachim Meyer To: linuxppc-embedded@ozlabs.org Subject: Re: Linux for ml310 Content-Type: text/plain; charset=iso-8859-15 List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi again I tried my compiled kernel this morning. I loaded my Bitstream onto the FPGA, then the zImage.elf via xmd: dow zIma= ge.elf. After I typed "run" I got foolowing message on an Terminal: ------------------------------------------------------------------------ loaded at: 00400000 004F219C board data at: 004F0120 004F019C relocated to: 00404048 004040C4 zimage at: 00404E39 004EF931 avail ram: 004F3000 10000000 Linux/PPC load: console=3DttyS0,9600 Uncompressing Linux...done. Now booting the kernel ------------------------------------------------------------------------ Doesn't look that bad I think. ;) The Question I have is of course why he stops there. Is it why He can't find a rootfs=3F Or would he say this in that case. I found someone with an similar Problem: http://lists.ppckernel.org/pipermail/ppckernel/2006-May/000026.html but I already use the xparameters=5Fml310 from my BSP. Where must I look for the error=3F There where some warnings when I compiled the kernel. Is this ok=3F Greets & THX Joachim PS: My xparameters=5Fml310.h --------------------------------------------------------------------------= ---------------------------------------------- /******************************************************************* * * CAUTION: This file is automatically generated by libgen. * Version: Xilinx EDK 9.1.02 EDK=5FJ=5FSP2.4 * DO NOT EDIT. * * Copyright (c) 2005 Xilinx, Inc. All rights reserved.=20 *=20 * Description: Driver parameters * *******************************************************************/ /* Definitions for driver UARTLITE */ #define XPAR=5FXUARTLITE=5FNUM=5FINSTANCES 1 /* Definitions for peripheral RS232=5FUART */ #define XPAR=5FRS232=5FUART=5FBASEADDR 0x40600000 #define XPAR=5FRS232=5FUART=5FHIGHADDR 0x4060FFFF #define XPAR=5FRS232=5FUART=5FDEVICE=5FID 0 #define XPAR=5FRS232=5FUART=5FBAUDRATE 9600 #define XPAR=5FRS232=5FUART=5FUSE=5FPARITY 0 #define XPAR=5FRS232=5FUART=5FODD=5FPARITY 0 #define XPAR=5FRS232=5FUART=5FDATA=5FBITS 8 /******************************************************************/ /* Definitions for driver SPI */ #define XPAR=5FXSPI=5FNUM=5FINSTANCES 1 /* Definitions for peripheral SPI=5FEEPROM */ #define XPAR=5FSPI=5FEEPROM=5FBASEADDR 0x4B308000 #define XPAR=5FSPI=5FEEPROM=5FHIGHADDR 0x4B30807F #define XPAR=5FSPI=5FEEPROM=5FDEVICE=5FID 0 #define XPAR=5FSPI=5FEEPROM=5FFIFO=5FEXIST 1 #define XPAR=5FSPI=5FEEPROM=5FSPI=5FSLAVE=5FONLY 0 #define XPAR=5FSPI=5FEEPROM=5FNUM=5FSS=5FBITS 1 /******************************************************************/ /* Definitions for driver PCI */ #define XPAR=5FXPCI=5FNUM=5FINSTANCES 1 /* Definitions for peripheral PCI32=5FBRIDGE */ #define XPAR=5FPCI32=5FBRIDGE=5FDEVICE=5FID 0 #define XPAR=5FPCI32=5FBRIDGE=5FBASEADDR 0x42600000 #define XPAR=5FPCI32=5FBRIDGE=5FHIGHADDR 0x4260FFFF #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5F0 0x00000000 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FLEN=5F0 7 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR2IPIF=5F0 0 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FENDIAN=5FTRANSLATE=5FEN=5F0 0 #define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FPREFETCH=5F0 1 #define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FSPACETYPE=5F0 1 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5F1 0xffffffff #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FLEN=5F1 20 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR2IPIF=5F1 0 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FENDIAN=5FTRANSLATE=5FEN=5F1 0 #define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FPREFETCH=5F1 1 #define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FSPACETYPE=5F1 1 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5F2 0xffffffff #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FLEN=5F2 20 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR2IPIF=5F2 0 #define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FENDIAN=5FTRANSLATE=5FEN=5F2 0 #define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FPREFETCH=5F2 1 #define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FSPACETYPE=5F2 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F0 0x60000000 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F0 0x7fffffff #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F0 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F0 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F0 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F0 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F1 0x54000000 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F1 0x57ffffff #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F1 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F1 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F1 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F1 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F2 0xffffffff #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F2 0x00000000 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F2 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F2 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F2 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F2 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F3 0xffffffff #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F3 0x00000000 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F3 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F3 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F3 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F3 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F4 0xffffffff #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F4 0x00000000 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F4 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F4 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F4 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F4 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F5 0xffffffff #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F5 0x00000000 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F5 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F5 0 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F5 1 #define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F5 1 #define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FBASEADDR 0xFFFFFFFF #define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FHIGHADDR 0x00000000 #define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FCHAN=5FTYPE 9 #define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FLENGTH=5FWIDTH 13 #define XPAR=5FPCI32=5FBRIDGE=5FBRIDGE=5FIDSEL=5FADDR=5FBIT 16 /******************************************************************/ #define XPAR=5FXSYSACE=5FMEM=5FWIDTH 8 /* Definitions for driver SYSACE */ #define XPAR=5FXSYSACE=5FNUM=5FINSTANCES 1 /* Definitions for peripheral SYSACE=5FCOMPACTFLASH */ #define XPAR=5FSYSACE=5FCOMPACTFLASH=5FBASEADDR 0x41800000 #define XPAR=5FSYSACE=5FCOMPACTFLASH=5FHIGHADDR 0x4180FFFF #define XPAR=5FSYSACE=5FCOMPACTFLASH=5FDEVICE=5FID 0 #define XPAR=5FSYSACE=5FCOMPACTFLASH=5FMEM=5FWIDTH 8 /******************************************************************/ #define XPAR=5FINTC=5FMAX=5FNUM=5FINTR=5FINPUTS 12 #define XPAR=5FXINTC=5FHAS=5FIPR 1 #define XPAR=5FXINTC=5FUSE=5FDCR 0 /* Definitions for driver INTC */ #define XPAR=5FXINTC=5FNUM=5FINSTANCES 1 /* Definitions for peripheral OPB=5FINTC=5F0 */ #define XPAR=5FOPB=5FINTC=5F0=5FBASEADDR 0x41200000 #define XPAR=5FOPB=5FINTC=5F0=5FHIGHADDR 0x4120FFFF #define XPAR=5FOPB=5FINTC=5F0=5FDEVICE=5FID 0 #define XPAR=5FOPB=5FINTC=5F0=5FKIND=5FOF=5FINTR 0x00000C00 /******************************************************************/ #define XPAR=5FINTC=5FSINGLE=5FBASEADDR 0x41200000 #define XPAR=5FINTC=5FSINGLE=5FHIGHADDR 0x4120FFFF #define XPAR=5FINTC=5FSINGLE=5FDEVICE=5FID XPAR=5FOPB=5FINTC=5F0=5FDEVICE=5FID #define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FSBR=5FINT=5FMASK 0X000001 #define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FSBR=5FINT=5FINTR 0 #define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTF=5FMASK 0X000002 #define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTF=5FINTR 1 #define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTE=5FMASK 0X000004 #define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTE=5FINTR 2 #define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTD=5FMASK 0X000008 #define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTD=5FINTR 3 #define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTC=5FMASK 0X000010 #define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTC=5FINTR 4 #define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTB=5FMASK 0X000020 #define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTB=5FINTR 5 #define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTA=5FMASK 0X000040 #define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTA=5FINTR 6 #define XPAR=5FSYSACE=5FCOMPACTFLASH=5FSYSACE=5FIRQ=5FMASK 0X000080 #define XPAR=5FOPB=5FINTC=5F0=5FSYSACE=5FCOMPACTFLASH=5FSYSACE=5FIRQ=5FINTR 7 #define XPAR=5FPCI32=5FBRIDGE=5FIP2INTC=5FIRPT=5FMASK 0X000100 #define XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIRPT=5FINTR 8 #define XPAR=5FSPI=5FEEPROM=5FIP2INTC=5FIRPT=5FMASK 0X000200 #define XPAR=5FOPB=5FINTC=5F0=5FSPI=5FEEPROM=5FIP2INTC=5FIRPT=5FINTR 9 #define XPAR=5FDDR=5FSDRAM=5F32MX64=5FIP2INTC=5FIRPT=5FMASK 0X000400 #define XPAR=5FOPB=5FINTC=5F0=5FDDR=5FSDRAM=5F32MX64=5FIP2INTC=5FIRPT=5FINTR 10 #define XPAR=5FRS232=5FUART=5FINTERRUPT=5FMASK 0X000800 #define XPAR=5FOPB=5FINTC=5F0=5FRS232=5FUART=5FINTERRUPT=5FINTR 11 /******************************************************************/ /* Definitions for driver DDR */ #define XPAR=5FXDDR=5FNUM=5FINSTANCES 1 /* Definitions for peripheral DDR=5FSDRAM=5F32MX64 */ #define XPAR=5FDDR=5FSDRAM=5F32MX64=5FECC=5FBASEADDR 0xFFFFFFFF #define XPAR=5FDDR=5FSDRAM=5F32MX64=5FECC=5FHIGHADDR 0x00000000 #define XPAR=5FDDR=5FSDRAM=5F32MX64=5FDEVICE=5FID 0 #define XPAR=5FDDR=5FSDRAM=5F32MX64=5FINCLUDE=5FECC=5FINTR 0 /******************************************************************/ /* Definitions for peripheral DDR=5FSDRAM=5F32MX64 */ #define XPAR=5FDDR=5FSDRAM=5F32MX64=5FMEM0=5FBASEADDR 0x00000000 #define XPAR=5FDDR=5FSDRAM=5F32MX64=5FMEM0=5FHIGHADDR 0x0FFFFFFF /******************************************************************/ /* Definitions for peripheral PLB=5FBRAM=5FIF=5FCNTLR=5F1 */ #define XPAR=5FPLB=5FBRAM=5FIF=5FCNTLR=5F1=5FBASEADDR 0xfffe0000 #define XPAR=5FPLB=5FBRAM=5FIF=5FCNTLR=5F1=5FHIGHADDR 0xffffffff /******************************************************************/ #define XPAR=5FCPU=5FPPC405=5FCORE=5FCLOCK=5FFREQ=5FHZ 100000000 /******************************************************************/ #define XPAR=5FCPU=5FID 0 #define XPAR=5FPPC405=5FID 0 #define XPAR=5FPPC405=5FCORE=5FCLOCK=5FFREQ=5FHZ 100000000 #define XPAR=5FPPC405=5FISOCM=5FDCR=5FBASEADDR 0x00000010 #define XPAR=5FPPC405=5FISOCM=5FDCR=5FHIGHADDR 0x00000013 #define XPAR=5FPPC405=5FDSOCM=5FDCR=5FBASEADDR 0x00000020 #define XPAR=5FPPC405=5FDSOCM=5FDCR=5FHIGHADDR 0x00000023 #define XPAR=5FPPC405=5FDISABLE=5FOPERAND=5FFORWARDING 1 #define XPAR=5FPPC405=5FDETERMINISTIC=5FMULT 0 #define XPAR=5FPPC405=5FMMU=5FENABLE 1 #define XPAR=5FPPC405=5FDCR=5FRESYNC 0 #define XPAR=5FPPC405=5FHW=5FVER "2.00.c" /******************************************************************/ /******************************************************************/ /* Cannonical Constant Names */ /******************************************************************/ #define XPAR=5FUARTLITE=5F0=5FBASEADDR XPAR=5FRS232=5FUART=5FBASEADDR #define XPAR=5FUARTLITE=5F0=5FHIGHADDR XPAR=5FRS232=5FUART=5FHIGHADDR #define XPAR=5FUARTLITE=5F0=5FDEVICE=5FID XPAR=5FRS232=5FUART=5FDEVICE=5FID /******************************************************************/ #define XPAR=5FSPI=5F0=5FBASEADDR XPAR=5FSPI=5FEEPROM=5FBASEADDR #define XPAR=5FSPI=5F0=5FHIGHADDR XPAR=5FSPI=5FEEPROM=5FHIGHADDR #define XPAR=5FSPI=5F0=5FFIFO=5FEXIST XPAR=5FSPI=5FEEPROM=5FFIFO=5FEXIST #define XPAR=5FSPI=5F0=5FSPI=5FSLAVE=5FONLY XPAR=5FSPI=5FEEPROM=5FSPI=5FSLAVE=5FONLY #define XPAR=5FSPI=5F0=5FNUM=5FSS=5FBITS XPAR=5FSPI=5FEEPROM=5FNUM=5FSS=5FBITS #define XPAR=5FSPI=5F0=5FDEVICE=5FID XPAR=5FSPI=5FEEPROM=5FDEVICE=5FID /******************************************************************/ #define XPAR=5FSYSACE=5F0=5FBASEADDR XPAR=5FSYSACE=5FCOMPACTFLASH=5FBASEADDR #define XPAR=5FSYSACE=5F0=5FHIGHADDR XPAR=5FSYSACE=5FCOMPACTFLASH=5FHIGHADDR #define XPAR=5FSYSACE=5F0=5FDEVICE=5FID XPAR=5FSYSACE=5FCOMPACTFLASH=5FDEVICE=5FID /******************************************************************/ #define XPAR=5FINTC=5F0=5FBASEADDR XPAR=5FOPB=5FINTC=5F0=5FBASEADDR #define XPAR=5FINTC=5F0=5FHIGHADDR XPAR=5FOPB=5FINTC=5F0=5FHIGHADDR #define XPAR=5FINTC=5F0=5FKIND=5FOF=5FINTR XPAR=5FOPB=5FINTC=5F0=5FKIND=5FOF=5FINTR #define XPAR=5FINTC=5F0=5FDEVICE=5FID XPAR=5FOPB=5FINTC=5F0=5FDEVICE=5FID /******************************************************************/ #define XPAR=5FINTC=5F0=5FSYSACE=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FSYSACE=5FCOMPACTFLASH=5FSY= SACE=5FIRQ=5FINTR #define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FA XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR= PT=5FINTR #define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FB XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR= PT=5FINTR #define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FC XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR= PT=5FINTR #define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FD XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR= PT=5FINTR #define XPAR=5FINTC=5F0=5FSPI=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FSPI=5FEEPROM=5FIP2INTC=5FIRPT=5FI= NTR #define XPAR=5FINTC=5F0=5FDDR=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FDDR=5FSDRAM=5F32MX64=5FIP2INTC=5F= IRPT=5FINTR #define XPAR=5FINTC=5F0=5FUARTLITE=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FRS232=5FUART=5FINTERRUPT= =5FINTR /******************************************************************/ #define XPAR=5FPLB=5FCLOCK=5FFREQ=5FHZ 100000000 #define XPAR=5FCORE=5FCLOCK=5FFREQ=5FHZ XPAR=5FCPU=5FPPC405=5FCORE=5FCLOCK=5FFREQ=5FHZ #define XPAR=5FDDR=5F0=5FSIZE 0x10000000 /******************************************************************/ #define XPAR=5FPCI=5F0=5FCLOCK=5FFREQ=5FHZ 0 /******************************************************************/ =5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F Jetzt neu! Sch=FCtzen Sie Ihren PC mit McAfee und WEB.DE. 30 Tage kostenlos testen. http://www.pc-sicherheit.web.de/startseite/=3Fmc=3D022220