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From: Anshuman Khandual <khandual@linux.vnet.ibm.com>
To: David Laight <David.Laight@ACULAB.COM>
Cc: Michael Ellerman <michaele@au1.ibm.com>,
	linux-kernel@vger.kernel.org,
	Stephane Eranian <eranian@google.com>,
	linuxppc-dev@ozlabs.org, Paul Mackerras <paulus@samba.org>,
	Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
	Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Subject: Re: [PATCH 02/10][v6] powerpc/Power7: detect load/store instructions
Date: Wed, 16 Oct 2013 15:08:01 +0530	[thread overview]
Message-ID: <525E5E79.6010905@linux.vnet.ibm.com> (raw)
In-Reply-To: <AE90C24D6B3A694183C094C60CF0A2F6026B738E@saturn3.aculab.com>

On 10/16/2013 01:55 PM, David Laight wrote:
>> Implement instr_is_load_store_2_06() to detect whether a given instruction
>> is one of the fixed-point or floating-point load/store instructions in the
>> POWER Instruction Set Architecture v2.06.
> ...

The op code encoding is dependent on the ISA version ? Does the basic load
and store instructions change with newer ISA versions ? BTW we have got a
newer version for the ISA "PowerISA_V2.07_PUBLIC.pdf" here at power.org

https://www.power.org/documentation/power-isa-version-2-07/

Does not sound like a good idea to analyse the instructions with functions
names which specify ISA version number. Besides, this function does not
belong to specific processor or platform. It has to be bit generic.
 
>> +int instr_is_load_store_2_06(const unsigned int *instr)
>> +{
>> +	unsigned int op, upper, lower;
>> +
>> +	op = instr_opcode(*instr);
>> +
>> +	if ((op >= 32 && op <= 58) || (op == 61 || op == 62))
>> +		return true;
>> +
>> +	if (op != 31)
>> +		return false;
>> +
>> +	upper = op >> 5;
>> +	lower = op & 0x1f;
>> +
>> +	/* Short circuit as many misses as we can */
>> +	if (lower < 3 || lower > 23)
>> +		return false;
>> +
>> +	if (lower == 3) {
>> +		if (upper >= 16)
>> +			return true;
>> +
>> +		return false;
>> +	}
>> +
>> +	if (lower == 7 || lower == 12)
>> +		return true;
>> +
>> +	if (lower >= 20) /* && lower <= 23 (implicit) */
>> +		return true;
>> +
>> +	return false;
>> +}
> 
> I can't help feeling the code could do with some comments about
> which actual instructions are selected where.

Yeah, I agree. At least which category of load-store instructions are
getting selected in each case.

  reply	other threads:[~2013-10-16  9:39 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-10-16  2:06 [PATCH 00/10][v6] powerpc/perf: Export memory hierarchy level in Power7/8 Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 01/10][v6] powerpc: Rename branch_opcode() to instr_opcode() Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 02/10][v6] powerpc/Power7: detect load/store instructions Sukadev Bhattiprolu
2013-10-16  8:25   ` David Laight
2013-10-16  9:38     ` Anshuman Khandual [this message]
2013-10-16 15:39       ` Sukadev Bhattiprolu
2013-10-16 15:27     ` Sukadev Bhattiprolu
2013-10-17 17:20       ` Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 03/10][v6] tools/perf: silence compiler warnings Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 04/10][v6] tools/perf: Remove local byteorder.h Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 05/10][v6] powerpc/perf: Remove PME_ prefix for power7 events Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 06/10][v6] powerpc/perf: Export Power8 generic events in sysfs Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 07/10][v6] powerpc/perf: Add Power8 event PM_MRK_GRP_CMPL to sysfs Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 08/10][v6] powerpc/perf: Define big-endian version of perf_mem_data_src Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 09/10][v6] powerpc/perf: Export Power8 memory hierarchy info to user space Sukadev Bhattiprolu
2013-10-16  2:06 ` [PATCH 10/10][v6] powerpc/perf: Export Power7 " Sukadev Bhattiprolu

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