Re: Ethernet driver for Linux kernel 2.6 running on ML403

["Grant Likely" <grant.likely@secretlab.ca>]

On 9/19/06, Grant Likely <grant.likely@secretlab.ca> wrote:
> On 9/19/06, Peter Korsgaard <jacmet@sunsite.dk> wrote:
> > >>>>> "GL" == Grant Likely <grant.likely@secretlab.ca> writes:
> > GL> If we reject the Xilinx driver code, then we either have to do
> > GL> without Xilinx support in mainline, or we need to write new
> > GL> drivers that address the above issues (support multiple IP
> > GL> versions, etc).  The Xilinx support in mainline right now does not
> > GL> use any Xilinx code.  (Xilinx PIC and UART).
> >
> > I think the best option is to simply forget about the Xilinx code,
> > see the FPGAs as any other PPC system and write normal device drivers
> > for it. Your platform bus stuff and my (to-be-mainlined) uartlite
> > driver is a first step in this direction..
>
> Too bad platform bus is sooo last year.  :p
>
> Time to hack device trees.

Avast!  After getting quizzed on IRC about this off-the-cuff comment,
I should probably clarify.  Since the Xilinx IP could be wired up to a
ublaze core or an off-chip processor, the drivers still need to use a
platform bus attachment to keep it all cross platform.

So, replace above comment with the following:

Populating the platform device with static code during initialization
is sooo last year.

Time to hack device trees to populate it instead.

:)

g.

-- 
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195