From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ug-out-1314.google.com (ug-out-1314.google.com [66.249.92.174]) by ozlabs.org (Postfix) with ESMTP id 0352467B56 for ; Wed, 20 Sep 2006 06:10:18 +1000 (EST) Received: by ug-out-1314.google.com with SMTP id 30so490250ugc for ; Tue, 19 Sep 2006 13:10:16 -0700 (PDT) Message-ID: <528646bc0609191310l240d9f94tb18415941f8b5d4f@mail.gmail.com> Date: Tue, 19 Sep 2006 14:10:16 -0600 From: "Grant Likely" Sender: glikely@gmail.com To: "Peter Korsgaard" Subject: Re: Ethernet driver for Linux kernel 2.6 running on ML403 In-Reply-To: <528646bc0609190717u1c7cd349m7e08e5bafd341c38@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed References: <002501c6d79e$cca7ee40$800101df@monstertop> <528646bc0609131852s41a8bc4ev44b84d68f51b1d2d@mail.gmail.com> <45093A94.2080407@dlasys.net> <200609141353.k8EDrkPN065101@penguin.ncube.com> <528646bc0609140734j2f7b008fy815f221677c5ac74@mail.gmail.com> <87hcz4z47p.fsf@sleipner.barco.com> <528646bc0609190717u1c7cd349m7e08e5bafd341c38@mail.gmail.com> Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 9/19/06, Grant Likely wrote: > On 9/19/06, Peter Korsgaard wrote: > > >>>>> "GL" == Grant Likely writes: > > GL> If we reject the Xilinx driver code, then we either have to do > > GL> without Xilinx support in mainline, or we need to write new > > GL> drivers that address the above issues (support multiple IP > > GL> versions, etc). The Xilinx support in mainline right now does not > > GL> use any Xilinx code. (Xilinx PIC and UART). > > > > I think the best option is to simply forget about the Xilinx code, > > see the FPGAs as any other PPC system and write normal device drivers > > for it. Your platform bus stuff and my (to-be-mainlined) uartlite > > driver is a first step in this direction.. > > Too bad platform bus is sooo last year. :p > > Time to hack device trees. Avast! After getting quizzed on IRC about this off-the-cuff comment, I should probably clarify. Since the Xilinx IP could be wired up to a ublaze core or an off-chip processor, the drivers still need to use a platform bus attachment to keep it all cross platform. So, replace above comment with the following: Populating the platform device with static code during initialization is sooo last year. Time to hack device trees to populate it instead. :) g. -- Grant Likely, B.Sc. P.Eng. Secret Lab Technologies Ltd. grant.likely@secretlab.ca (403) 399-0195