From: "Grant Likely" <grant.likely@secretlab.ca>
To: "Mohammad Sadegh Sadri" <mamsadegh@hotmail.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )
Date: Tue, 24 Apr 2007 08:59:37 -0600 [thread overview]
Message-ID: <528646bc0704240759g1dd30c68qd518c0fd3aa9ea9f@mail.gmail.com> (raw)
In-Reply-To: <BAY115-W63BB55D8630825D7BBEAFB24A0@phx.gbl>
On 4/24/07, Mohammad Sadegh Sadri <mamsadegh@hotmail.com> wrote:
>
>
> what about the cache?
> Does the current kernel use the cache efficiently?
Yes, the caches work and are turned on by the kernel.
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
next prev parent reply other threads:[~2007-04-24 14:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-04-24 14:52 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM ) Mohammad Sadegh Sadri
2007-04-24 14:59 ` Grant Likely [this message]
-- strict thread matches above, loose matches on Subject: below --
2007-04-24 15:37 Mohammad Sadegh Sadri
2007-04-24 17:43 ` Grant Likely
2007-04-25 19:37 ` jozsef imrek
2007-04-24 12:52 Mohammad Sadegh Sadri
2007-04-24 13:55 ` Grant Likely
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