2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[Mohammad Sadegh Sadri]

Hi all,

Just a very simple question about the 2.6 kerenl,

suppose that in my base system I have included 8kbytes of memory for DS OCM=
 and 8K for IS OCM,
I have generated the proper xparameters.h and copied it into kernel

Now I want to know if kernel will use this portion of memory during it's op=
eration?
Does this increase performance?

thanks

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Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[Grant Likely]

On 4/24/07, Mohammad Sadegh Sadri <mamsadegh@hotmail.com> wrote:
>
> suppose that in my base system I have included 8kbytes of memory for DS OCM and 8K for IS OCM,
> I have generated the proper xparameters.h and copied it into kernel
>
> Now I want to know if kernel will use this portion of memory during it's operation?
> Does this increase performance?

No, it won't use that memory as general purpose RAM.  You can make use
of it in device drivers (ie. for DMA space), but you'll need to write
the code to support it.

Cheers,
g.

-- 
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

RE: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[Mohammad Sadegh Sadri]

what about the cache?
Does the current kernel use the cache efficiently?



----------------------------------------
> Date: Tue, 24 Apr 2007 07:55:48 -0600
> From: grant.likely@secretlab.ca
> To: mamsadegh@hotmail.com
> Subject: Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory contro=
llers ( DSOCM and ISOCM )
> CC: linuxppc-embedded@ozlabs.org
>=20
> On 4/24/07, Mohammad Sadegh Sadri  wrote:
> >
> > suppose that in my base system I have included 8kbytes of memory for DS=
 OCM and 8K for IS OCM,
> > I have generated the proper xparameters.h and copied it into kernel
> >
> > Now I want to know if kernel will use this portion of memory during it'=
s operation?
> > Does this increase performance?
>=20
> No, it won't use that memory as general purpose RAM.  You can make use
> of it in device drivers (ie. for DMA space), but you'll need to write
> the code to support it.
>=20
> Cheers,
> g.
>=20
> --=20
> Grant Likely, B.Sc. P.Eng.
> Secret Lab Technologies Ltd.
> grant.likely@secretlab.ca
> (403) 399-0195

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Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[Grant Likely]

On 4/24/07, Mohammad Sadegh Sadri <mamsadegh@hotmail.com> wrote:
>
>
> what about the cache?
> Does the current kernel use the cache efficiently?

Yes, the caches work and are turned on by the kernel.

g.

-- 
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

RE: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[Mohammad Sadegh Sadri]

Then in mailing list I saw some where that AVNET mini-modules are using a v=
ersion of FX12 FPGA which has problem with PPC caches and as the solution t=
he caches should be off.

Does the kernel always turns on the caches? Or If I choose in the base syst=
em builder to not to use caches, the kernel will not use them?=20

Any special config parameter for this in xparameters.h?

thanks



----------------------------------------
> Date: Tue, 24 Apr 2007 08:59:37 -0600
> From: grant.likely@secretlab.ca
> To: mamsadegh@hotmail.com
> Subject: Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory contro=
llers ( DSOCM and ISOCM )
> CC: linuxppc-embedded@ozlabs.org
>=20
> On 4/24/07, Mohammad Sadegh Sadri  wrote:
> >
> >
> > what about the cache?
> > Does the current kernel use the cache efficiently?
>=20
> Yes, the caches work and are turned on by the kernel.
>=20
> g.
>=20
> --=20
> Grant Likely, B.Sc. P.Eng.
> Secret Lab Technologies Ltd.
> grant.likely@secretlab.ca
> (403) 399-0195

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Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[Grant Likely]

On 4/24/07, Mohammad Sadegh Sadri <mamsadegh@hotmail.com> wrote:
>
> Then in mailing list I saw some where that AVNET mini-modules are using a version of FX12 FPGA which has problem with PPC caches and as the solution the caches should be off.
>
> Does the kernel always turns on the caches? Or If I choose in the base system builder to not to use caches, the kernel will not use them?

I'm pretty sure that specific issue was due to a certain version of
silicon.  You'll need to check the Xilinx errata sheets.

>
> Any special config parameter for this in xparameters.h?

No.  You need to hack the startup code to turn off caches.

g.

-- 
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

RE: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[jozsef imrek]

On Tue, 24 Apr 2007, Mohammad Sadegh Sadri wrote:

> Then in mailing list I saw some where that AVNET mini-modules are using 
> a version of FX12 FPGA which has problem with PPC caches and as the 
> solution the caches should be off.

i think the relevant errata is this:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=20658
see solution 13.


as far as i understand the problem was caused by the plb2opb bridge
used in the design. the bridge was necessary because the plb_ddr
controller in earlier EDKs did not support the 16bit DDR memory
present on the avnet (earlier memec) minimodule, therefore you had to
use an opb_ddr controller.

however, the plb_ddr present in recent EDKs (ie plb_ddr v2.00.a)
_does_ support 16bit wide memory, therefore you do not need the
plb2opb bridge.

so as long as you are using the plb_ddr controller, and you are
disabling cache for other devices on the opb bus you should be
safe.



could someone with more authentic knowledge confirm this? anyone
from xilinx/avnet?



-- 
mazsi

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