From: "Grant Likely" <grant.likely@secretlab.ca>
To: "Mohammad Sadegh Sadri" <mamsadegh@hotmail.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )
Date: Tue, 24 Apr 2007 11:43:26 -0600 [thread overview]
Message-ID: <528646bc0704241043u5d0c397cnee16a343b90fdf09@mail.gmail.com> (raw)
In-Reply-To: <BAY115-W14E65268F6A301B98090EEB24A0@phx.gbl>
On 4/24/07, Mohammad Sadegh Sadri <mamsadegh@hotmail.com> wrote:
>
> Then in mailing list I saw some where that AVNET mini-modules are using a version of FX12 FPGA which has problem with PPC caches and as the solution the caches should be off.
>
> Does the kernel always turns on the caches? Or If I choose in the base system builder to not to use caches, the kernel will not use them?
I'm pretty sure that specific issue was due to a certain version of
silicon. You'll need to check the Xilinx errata sheets.
>
> Any special config parameter for this in xparameters.h?
No. You need to hack the startup code to turn off caches.
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
next prev parent reply other threads:[~2007-04-24 17:43 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-04-24 15:37 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM ) Mohammad Sadegh Sadri
2007-04-24 17:43 ` Grant Likely [this message]
2007-04-25 19:37 ` jozsef imrek
-- strict thread matches above, loose matches on Subject: below --
2007-04-24 14:52 Mohammad Sadegh Sadri
2007-04-24 14:59 ` Grant Likely
2007-04-24 12:52 Mohammad Sadegh Sadri
2007-04-24 13:55 ` Grant Likely
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