From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ug-out-1314.google.com (ug-out-1314.google.com [66.249.92.173]) by ozlabs.org (Postfix) with ESMTP id 143BADDF54 for ; Wed, 25 Apr 2007 03:43:27 +1000 (EST) Received: by ug-out-1314.google.com with SMTP id k3so189235ugf for ; Tue, 24 Apr 2007 10:43:26 -0700 (PDT) Message-ID: <528646bc0704241043u5d0c397cnee16a343b90fdf09@mail.gmail.com> Date: Tue, 24 Apr 2007 11:43:26 -0600 From: "Grant Likely" Sender: glikely@gmail.com To: "Mohammad Sadegh Sadri" Subject: Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM ) In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed References: Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 4/24/07, Mohammad Sadegh Sadri wrote: > > Then in mailing list I saw some where that AVNET mini-modules are using a version of FX12 FPGA which has problem with PPC caches and as the solution the caches should be off. > > Does the kernel always turns on the caches? Or If I choose in the base system builder to not to use caches, the kernel will not use them? I'm pretty sure that specific issue was due to a certain version of silicon. You'll need to check the Xilinx errata sheets. > > Any special config parameter for this in xparameters.h? No. You need to hack the startup code to turn off caches. g. -- Grant Likely, B.Sc. P.Eng. Secret Lab Technologies Ltd. grant.likely@secretlab.ca (403) 399-0195