Re: [RFC] uartlite driver MicroBlaze compatability

["Grant Likely" <grant.likely@secretlab.ca>]

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On 5/1/07, John Williams <jwilliams@itee.uq.edu.au> wrote:
> Grant Likely wrote:
> > However, the uartlite is *not* an 8250.  The 8250 turns up all over
> > the place and it's registers are defined as 8 bit wide.  The
> > offset-by-3 stuff is part of the plat_serial8250_port structure which
> > is also used to specify .regshift (increment between registers).
> > Whereas the UARTLITE is defined as a 32 bit device and it doesn't show
> > up in anywhere near as many designs.  Registers are always 4 bytes
> > wide and are always located at multiples of 4 bytes off the base

Hmm, I think I was smoking something last night.  Address used for 8
bit access should not be affected by CPU endianess.  After David's
comments, I reread the uartlite documentation.  The current design is
definately for 32bit OPB bus connections, but it looks like there is a
posibility for xilinx to add a 16 or 8 bit attachment.  Since the
uartlite design explicitly supports 8, 16 and 32 bit access, sticking
with 8 bit io may be the safest.  However, I still think the
application of the 3 byte offset should be done in the driver, and not
in the platform bus registration.

I've reworked the patch with the following changes
- remove 3 byte offset from platform bus registration.
- added ulite_in/ulite_out macros to make changing bus attachment
details simpler if xilinx changes the uartlite design.
- stick with 8 bit IO.

Tested on PPC.  John, can you please test on microblaze?

Cheers,
g.

-- 
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

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