On 12/28/2013 01:41 PM, Gavin Hu wrote:
> Hi
>
> I notice that there is a pair ppc instructions lwarx and stwcx used to 
> atomtic operation for instance, atomic_inc/atomic_dec.
>
> In some ppc manuals, they more emphasize its mechanism is that lwarx 
> can reseve the target memory address preventing other CORE from 
> modifying it.
>
> I assume that there is atomtic operation executing on the CORE0 in a 
> multicore system. In this situation, does the CORE0 disable the local 
> HW interrupt?
> Can the executing process from the beginning of lwarx and end of stwcx 
> be interrupted by HW interruptions/exceptions? Anyway, they are two 
> assembly instructions.

It should just like other arch, the processor should response any 
interrupt after the execution of a instruction, so the local HW 
interrupt is not disabled.

Thanks
Wei
>
>  Thanks a lot!
>
> "1:    lwarx    %0,0,%2        # atomic_inc\n\
>     addic    %0,%0,1\n"
> "    stwcx.    %0,0,%2 \n\
>
>
> BR
> Gavin. Hu
>
>
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