MPC8245 reset register

MPC8245 reset register

[Reeve Yang]

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Can anyone tell me which register should I use to do soft reset on MPC8241/5
CPU? I searched its manuall but only find EPIC to send SRESET exception on
offset 0x41090.

Thanks.

- Reeve

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Re: MPC8245 reset register

[Jon Scully]

On 9/2/06, Reeve Yang <yang.reeve@gmail.com> wrote:
> Can anyone tell me which register should I use to do soft reset on MPC8241/5
> CPU? I searched its manuall but only find EPIC to send SRESET exception on
> offset 0x41090.
>
>  Thanks.
>
>  - Reeve
>

Use the reset instruction (RST in assembly).

Re: MPC8245 reset register

[Reeve Yang]

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Hi Jon,

Could you elaborate it a bit? I wrote 0x1 to PI register, but CPU hangs
without resetting. I'm kind of curious what's the proper way to reset the
8245 CPU? For anyone who doesn't know MPC8245, which is 603e core.

Thanks a lot.

- Reeve

On 9/2/06, Jon Scully <jonscully@gmail.com> wrote:
>
> On 9/2/06, Reeve Yang <yang.reeve@gmail.com> wrote:
> > Can anyone tell me which register should I use to do soft reset on
> MPC8241/5
> > CPU? I searched its manuall but only find EPIC to send SRESET exception
> on
> > offset 0x41090.
> >
> >  Thanks.
> >
> >  - Reeve
> >
>
> Use the reset instruction (RST in assembly).
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>

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Re: MPC8245 reset register

[Jon Scully]

On 9/5/06, Reeve Yang <yang.reeve@gmail.com> wrote:
>  I'm kind of curious what's the proper way to reset the
> 8245 CPU? For anyone who doesn't know MPC8245, which is 603e core.

You could starve the watchdog (assuming SWE=1 in SYPCR).  If you own
the hardware design, you could add an addressable WO latch (FPGA) that
asserts reset for the right number of clock cycles (what I would
normally provide or ask for in a design -- but *only* during
development).  Otherwise... If this is for development purposes,
consider using JTAG (Boundary Scan) to control /SRESET.

(My reference to RST was supposed to be humorous -- as in, remember
the good old days when you could do that in S/W?! ('RST 7' in Z80 &
8085)  Sorry for my bad humor.)

Re: MPC8245 reset register

[Reeve Yang]

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LoL, my bad not understanding the humor.

This becomes an interesting topic. I looked at different CPUs, it seems
everyone uses different method to reset itself, and there is no uniformed or
easy for 603e. I searched on google but didn't see anyone have similiar
concern. Actually lots of boxes/systems using MPC8245, why nobody cares
about it? :)

To use watchdog timeout, or gpio port to assert reset line on CPU are not
flexible enough. If using watchdog, I have to enable watchdog and reduce the
timeout length (if it's too long). If using some GPIO device, I'll have to
rely on i2c bus or whatever io interface to write data. Acutally our system
has RESET by a GPIO(PCA9556) port.

Interesting enough, I resolved the problem by writing a data to an invalid
address with hoping for a machine check exception (in fact this is what
u-boot does). Would it be good to make it as a stardard "restart" function
in mpc10x_common.c? If it's acceptable I could send out my patch.

- Reeve

On 9/6/06, Jon Scully <jonscully@gmail.com> wrote:
>
> On 9/5/06, Reeve Yang <yang.reeve@gmail.com> wrote:
> >  I'm kind of curious what's the proper way to reset the
> > 8245 CPU? For anyone who doesn't know MPC8245, which is 603e core.
>
> You could starve the watchdog (assuming SWE=1 in SYPCR).  If you own
> the hardware design, you could add an addressable WO latch (FPGA) that
> asserts reset for the right number of clock cycles (what I would
> normally provide or ask for in a design -- but *only* during
> development).  Otherwise... If this is for development purposes,
> consider using JTAG (Boundary Scan) to control /SRESET.
>
> (My reference to RST was supposed to be humorous -- as in, remember
> the good old days when you could do that in S/W?! ('RST 7' in Z80 &
> 8085)  Sorry for my bad humor.)
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>

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