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Date: Mon, 2 Jun 2014 15:48:23 +0300
From: Tudor Laurentiu <b10716@freescale.com>
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To: Scott Wood <scottwood@freescale.com>
Subject: Re: [PATCH v2] powerpc/booke64: wrap tlb lock and search in htw miss
 with FTR_SMT
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On 05/31/2014 01:45 AM, Scott Wood wrote:
> From: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
>
> Virtualized environments may expose a e6500 dual-threaded core
> as two single-threaded e6500 cores. Take advantage of this
> and get rid of the tlb lock and the trap-causing tlbsx in
> the htw miss handler by guarding with CPU_FTR_SMT, as it's
> already being done in the bolted tlb1 miss handler.
>
> As seen in the results below, measurements done with lmbench
> random memory access latency test running under Freescale's
> Embedded Hypervisor, there is a ~34% improvement.
>
> Memory latencies in nanoseconds - smaller is better
>      (WARNING - may not be correct, check graphs)
> ----------------------------------------------------
> Host       Mhz   L1 $   L2 $    Main mem    Rand mem
> ---------  ---   ----   ----    --------    --------
> smt       1665 1.8020   13.2    83.0         1149.7
> nosmt     1665 1.8020   13.2    83.0          758.1
>
> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
> Cc: Scott Wood <scottwood@freescale.com>
> [scottwood@freescale.com: commit message tweak]
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> v2:
>   - s/expose/may expose/ in commit message
>   - rebased onto my patch queue to resolve conflict

Thanks!

>   - resent since the original didn't make it to the list archives
>     or patchwork.

The only thing i can think of is that maybe i've misspelled the mailing 
list address ...

---
Best Regards, Laurentiu