From: Anshuman Khandual <khandual@linux.vnet.ibm.com>
To: linuxppc-dev@ozlabs.org
Cc: Michael Ellerman <michael@ellerman.id.au>
Subject: Re: [PATCH V3] powerpc, xmon: Enable HW instruction breakpoint on POWER8
Date: Mon, 27 Oct 2014 11:50:00 +0530 [thread overview]
Message-ID: <544DE410.8090009@linux.vnet.ibm.com> (raw)
In-Reply-To: <1412855321-21276-1-git-send-email-khandual@linux.vnet.ibm.com>
On 10/09/2014 05:18 PM, Anshuman Khandual wrote:
> This patch enables support for hardware instruction breakpoints
> on POWER8 with the help of a new register CIABR (Completed
> Instruction Address Breakpoint Register). With this patch, single
> hardware instruction breakpoint can be added and cleared during
> any active xmon debug session. This hardware based instruction
> breakpoint mechanism works correctly along with the existing TRAP
> based instruction breakpoints available on xmon.
Hey Michael,
Any updates on this patch ?
prev parent reply other threads:[~2014-10-27 6:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-09 11:48 [PATCH V3] powerpc, xmon: Enable HW instruction breakpoint on POWER8 Anshuman Khandual
2014-10-27 6:20 ` Anshuman Khandual [this message]
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