* [PATCH v2 1/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan
2014-10-28 9:15 [PATCH v2 0/4] dt/bindings: Introduce the FSL B/QMan Emil Medve
@ 2014-10-28 9:15 ` Emil Medve
2014-10-28 14:39 ` Kumar Gala
[not found] ` <5DC63911-AD43-4EDA-8675-8A28EDC3F491__16064.0273978517$1414507192$gmane$org@codeaurora.org>
2014-10-28 9:15 ` [PATCH v2 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s) Emil Medve
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Emil Medve @ 2014-10-28 9:15 UTC (permalink / raw)
To: scottwood, galak, corbet, robh+dt, ijc+devicetree, galak,
pawel.moll, mark.rutland, grant.likely, Geoff.Thorpe,
linuxppc-dev, devicetree, linux-doc
Cc: Emil Medve
The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
BMan supports hardware allocation and deallocation of buffers belonging to
pools originally created by software with configurable depletion thresholds.
This binding covers the CCSR space programming model
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I3ec479bfb3c91951e96902f091f5d7d2adbef3b2
---
.../devicetree/bindings/powerpc/fsl/bman.txt | 95 ++++++++++++++++++++++
1 file changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/bman.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/bman.txt b/Documentation/devicetree/bindings/powerpc/fsl/bman.txt
new file mode 100644
index 0000000..d3fd1e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/bman.txt
@@ -0,0 +1,95 @@
+QorIQ DPAA Buffer Manager Device Tree Bindings
+
+Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
+
+CONTENTS
+
+ - BMan Node
+ - BMan Private Memory Node
+ - Example
+
+BMan Node
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,bman"
+ May include "fsl,<SoC>-bman"
+
+- reg
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Registers region within the CCSR address space
+
+- interrupts
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Standard property. The error interrupt
+
+- fsl,liodn
+ Usage: See pamu.txt
+ Value type: <prop-encoded-array>
+ Definition: PAMU property used for static LIODN assignment
+
+- fsl,iommu-parent
+ Usage: See pamu.txt
+ Value type: <phandle>
+ Definition: PAMU property used for dynamic LIODN assignment
+
+ For additional details about the PAMU/LIODN binding(s) see pamu.txt
+
+BMan Private Memory Node
+
+BMan requires a contiguous range of physical memory used for the backing store
+for BMan Free Buffer Proxy Records. This memory is reserved/allocated as a node
+under the /reserved-memory node
+
+The BMan FBPR memory node must be named "bman-fbpr"
+
+PROPERTIES
+
+- compatible
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must inclide "fsl,bman-fbpr"
+
+The following constraints are relevant to the FBPR private memory:
+ - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
+ 16 GiB
+ - The alignment must be a muliptle of the memory size
+
+The size of the FBPR must be chosen by observing the hardware features configured
+via the RCW and that are relevant to a specific board (e.g. number of MAC(s)
+pinned-out, number of offline/host command FMan ports, etc.). The size configured
+in the DT must reflect the hardware capabilities and not the specific needs of an
+application
+
+For additional details about reserved memory regions see reserved-memory.txt
+
+EXAMPLE
+
+The example below shows a BMan FBPR dynamic allocation memory node
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman-fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0xf 0xffffffff>;
+ size = <0 0x1000000>;
+ alignment = <0 0x1000000>;
+ };
+ };
+
+The example below shows a (P4080) BMan CCSR-space node
+
+ bman@31a000 {
+ compatible = "fsl,bman";
+ reg = <0x31a000 0x1000>;
+ interrupts = <16 2 1 2>;
+ fsl,liodn = <0x17>;
+ };
--
2.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan
2014-10-28 9:15 ` [PATCH v2 1/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan Emil Medve
@ 2014-10-28 14:39 ` Kumar Gala
[not found] ` <5DC63911-AD43-4EDA-8675-8A28EDC3F491__16064.0273978517$1414507192$gmane$org@codeaurora.org>
1 sibling, 0 replies; 9+ messages in thread
From: Kumar Gala @ 2014-10-28 14:39 UTC (permalink / raw)
To: Emil Medve
Cc: mark.rutland, devicetree, pawel.moll, ijc+devicetree,
Geoff.Thorpe, corbet, linux-doc, linuxppc-dev, grant.likely,
robh+dt, scottwood
On Oct 28, 2014, at 4:15 AM, Emil Medve <Emilian.Medve@freescale.com> =
wrote:
> The Buffer Manager is part of the Data-Path Acceleration Architecture =
(DPAA).
> BMan supports hardware allocation and deallocation of buffers =
belonging to
> pools originally created by software with configurable depletion =
thresholds.
> This binding covers the CCSR space programming model
>=20
> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
> Change-Id: I3ec479bfb3c91951e96902f091f5d7d2adbef3b2
> ---
> .../devicetree/bindings/powerpc/fsl/bman.txt | 95 =
++++++++++++++++++++++
> 1 file changed, 95 insertions(+)
> create mode 100644 =
Documentation/devicetree/bindings/powerpc/fsl/bman.txt
Should these really be in bindings/powerpc/fsl, aren=92t you guys using =
this on ARM SoCs as well?
I can=92t remember if the TI guys had a HW allocator as part of their =
similar HW. If so, possibly worth while to see where they have their =
binding.
>=20
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/bman.txt =
b/Documentation/devicetree/bindings/powerpc/fsl/bman.txt
> new file mode 100644
> index 0000000..d3fd1e3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/bman.txt
> @@ -0,0 +1,95 @@
> +QorIQ DPAA Buffer Manager Device Tree Bindings
> +
> +Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
> +
> +CONTENTS
> +
> + - BMan Node
> + - BMan Private Memory Node
> + - Example
> +
> +BMan Node
> +
> +PROPERTIES
> +
> +- compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must include "fsl,bman"
> + May include "fsl,<SoC>-bman"
> +
> +- reg
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: Registers region within the CCSR address space
> +
> +- interrupts
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: Standard property. The error interrupt
> +
> +- fsl,liodn
> + Usage: See pamu.txt
> + Value type: <prop-encoded-array>
> + Definition: PAMU property used for static LIODN assignment
> +
> +- fsl,iommu-parent
> + Usage: See pamu.txt
> + Value type: <phandle>
> + Definition: PAMU property used for dynamic LIODN assignment
> +
> + For additional details about the PAMU/LIODN binding(s) see =
pamu.txt
> +
> +BMan Private Memory Node
> +
> +BMan requires a contiguous range of physical memory used for the =
backing store
> +for BMan Free Buffer Proxy Records. This memory is reserved/allocated =
as a node
=85 Proxy Records (FBPR). This
[ so we get context for the acronym used later ]
> +under the /reserved-memory node
> +
> +The BMan FBPR memory node must be named "bman-fbpr"
> +
> +PROPERTIES
> +
> +- compatible
> + Usage: required
> + Value type: <stringlist>
> + Definition: Must inclide "fsl,bman-fbpr"
> +
> +The following constraints are relevant to the FBPR private memory:
> + - The size must be 2^(size + 1), with size =3D 11..33. That is 4 =
KiB to
> + 16 GiB
> + - The alignment must be a muliptle of the memory size
> +
> +The size of the FBPR must be chosen by observing the hardware =
features configured
> +via the RCW and that are relevant to a specific board (e.g. number of =
MAC(s)
> +pinned-out, number of offline/host command FMan ports, etc.). The =
size configured
> +in the DT must reflect the hardware capabilities and not the specific =
needs of an
> +application
RCW doesn=92t have any context here
> +
> +For additional details about reserved memory regions see =
reserved-memory.txt
> +
> +EXAMPLE
> +
> +The example below shows a BMan FBPR dynamic allocation memory node
> +
> + reserved-memory {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + ranges;
> +
> + bman-fbpr {
> + compatible =3D "fsl,bman-fbpr";
> + alloc-ranges =3D <0 0 0xf 0xffffffff>;
> + size =3D <0 0x1000000>;
> + alignment =3D <0 0x1000000>;
> + };
> + };
> +
> +The example below shows a (P4080) BMan CCSR-space node
> +
> + bman@31a000 {
> + compatible =3D "fsl,bman";
> + reg =3D <0x31a000 0x1000>;
> + interrupts =3D <16 2 1 2>;
> + fsl,liodn =3D <0x17>;
no fsl,iommu-parent in the example?
> + };
Do you not need a phandle between the bman and the memory node?
- k
--=20
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora =
Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread[parent not found: <5DC63911-AD43-4EDA-8675-8A28EDC3F491__16064.0273978517$1414507192$gmane$org@codeaurora.org>]
* Re: [PATCH v2 1/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan
[not found] ` <5DC63911-AD43-4EDA-8675-8A28EDC3F491__16064.0273978517$1414507192$gmane$org@codeaurora.org>
@ 2014-10-29 21:16 ` Emil Medve
0 siblings, 0 replies; 9+ messages in thread
From: Emil Medve @ 2014-10-29 21:16 UTC (permalink / raw)
To: Kumar Gala
Cc: mark.rutland, devicetree, pawel.moll, corbet, Geoff.Thorpe,
ijc+devicetree, linux-doc, scottwood, linuxppc-dev, robh+dt,
grant.likely
Hello Kumar,
Thanks for taking the time to review this
On 10/28/2014 09:39 AM, Kumar Gala wrote:
> On Oct 28, 2014, at 4:15 AM, Emil Medve <Emilian.Medve@freescale.com> wrote:
>> The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
>> BMan supports hardware allocation and deallocation of buffers belonging to
>> pools originally created by software with configurable depletion thresholds.
>> This binding covers the CCSR space programming model
>>
>> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
>> Change-Id: I3ec479bfb3c91951e96902f091f5d7d2adbef3b2
>> ---
>> .../devicetree/bindings/powerpc/fsl/bman.txt | 95 ++++++++++++++++++++++
>> 1 file changed, 95 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/bman.txt
>
> Should these really be in bindings/powerpc/fsl, aren’t you guys using this on ARM SoCs as well?
We do, however, I didn't have any exposure yet to how the DPAA was
integrated there. From what I hear the biggest difference is in the
IOMMU area. Upstreaming the DPAA has been long overdue and I'd like to
make some progress with it as is on the PowerPC SoC(s)
> I can’t remember if the TI guys had a HW allocator as part of their
> similar HW. If so, possibly worth while to see where they have their
> binding.
Seems their data-path bindings are in
Documentation/devicetree/bindings/soc. I can move the B/QMan there and
it would level the way for the ARM SoC(s) with the DPAA
>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/bman.txt b/Documentation/devicetree/bindings/powerpc/fsl/bman.txt
>> new file mode 100644
>> index 0000000..d3fd1e3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/powerpc/fsl/bman.txt
>> @@ -0,0 +1,95 @@
>> +QorIQ DPAA Buffer Manager Device Tree Bindings
>> +
>> +Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
>> +
>> +CONTENTS
>> +
>> + - BMan Node
>> + - BMan Private Memory Node
>> + - Example
>> +
>> +BMan Node
>> +
>> +PROPERTIES
>> +
>> +- compatible
>> + Usage: Required
>> + Value type: <stringlist>
>> + Definition: Must include "fsl,bman"
>> + May include "fsl,<SoC>-bman"
>> +
>> +- reg
>> + Usage: Required
>> + Value type: <prop-encoded-array>
>> + Definition: Registers region within the CCSR address space
>> +
>> +- interrupts
>> + Usage: Required
>> + Value type: <prop-encoded-array>
>> + Definition: Standard property. The error interrupt
>> +
>> +- fsl,liodn
>> + Usage: See pamu.txt
>> + Value type: <prop-encoded-array>
>> + Definition: PAMU property used for static LIODN assignment
>> +
>> +- fsl,iommu-parent
>> + Usage: See pamu.txt
>> + Value type: <phandle>
>> + Definition: PAMU property used for dynamic LIODN assignment
>> +
>> + For additional details about the PAMU/LIODN binding(s) see pamu.txt
>> +
>> +BMan Private Memory Node
>> +
>> +BMan requires a contiguous range of physical memory used for the backing store
>> +for BMan Free Buffer Proxy Records. This memory is reserved/allocated as a node
>
> … Proxy Records (FBPR). This
>
> [ so we get context for the acronym used later ]
Will do
>> +under the /reserved-memory node
>> +
>> +The BMan FBPR memory node must be named "bman-fbpr"
>> +
>> +PROPERTIES
>> +
>> +- compatible
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: Must inclide "fsl,bman-fbpr"
>> +
>> +The following constraints are relevant to the FBPR private memory:
>> + - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
>> + 16 GiB
>> + - The alignment must be a muliptle of the memory size
>> +
>> +The size of the FBPR must be chosen by observing the hardware features configured
>> +via the RCW and that are relevant to a specific board (e.g. number of MAC(s)
>> +pinned-out, number of offline/host command FMan ports, etc.). The size configured
>> +in the DT must reflect the hardware capabilities and not the specific needs of an
>> +application
>
> RCW doesn’t have any context here
Will expand it
>> +For additional details about reserved memory regions see reserved-memory.txt
>> +
>> +EXAMPLE
>> +
>> +The example below shows a BMan FBPR dynamic allocation memory node
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + bman-fbpr {
>> + compatible = "fsl,bman-fbpr";
>> + alloc-ranges = <0 0 0xf 0xffffffff>;
>> + size = <0 0x1000000>;
>> + alignment = <0 0x1000000>;
>> + };
>> + };
>> +
>> +The example below shows a (P4080) BMan CCSR-space node
>> +
>> + bman@31a000 {
>> + compatible = "fsl,bman";
>> + reg = <0x31a000 0x1000>;
>> + interrupts = <16 2 1 2>;
>> + fsl,liodn = <0x17>;
>
> no fsl,iommu-parent in the example?
Using the PAMU/IOMMU topology (for dynamic LIODN allocation) is not
working yet in the PAMU driver (not even programming only the parent
PAMU with the static LIODN from the node) so I'm not quite in the habit
of sprinkling those around. I'll add them into the examples
>> + };
>
> Do you not need a phandle between the bman and the memory node?
Nope. And I'm thinking two reasons: (1) (if it gets to it) unique
compatible(s) for the reserved-memory nodes and (2)
RESERVEDMEM_OF_DECLARE() takes care to connect the dots based on said
compatible(s)
Cheers,
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)
2014-10-28 9:15 [PATCH v2 0/4] dt/bindings: Introduce the FSL B/QMan Emil Medve
2014-10-28 9:15 ` [PATCH v2 1/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan Emil Medve
@ 2014-10-28 9:15 ` Emil Medve
2014-10-28 14:41 ` Kumar Gala
[not found] ` <044D58B4-690A-4CEA-B2DB-8AF4549D4AE2__43711.2007676207$1414507333$gmane$org@codeaurora.org>
2014-10-28 9:15 ` [PATCH v2 3/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan Emil Medve
2014-10-28 9:15 ` [PATCH v2 4/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s) Emil Medve
3 siblings, 2 replies; 9+ messages in thread
From: Emil Medve @ 2014-10-28 9:15 UTC (permalink / raw)
To: scottwood, galak, corbet, robh+dt, ijc+devicetree, galak,
pawel.moll, mark.rutland, grant.likely, Geoff.Thorpe,
linuxppc-dev, devicetree, linux-doc
Cc: Emil Medve
Portals are memory mapped interfaces to BMan that allow low-latency,
lock-less interaction by software running on processor cores, accelerators
and network interfaces with the BMan
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I6d245ffc14ba3d0e91d403ac7c3b91b75a9e6a95
---
.../bindings/powerpc/fsl/bman-portals.txt | 52 ++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
new file mode 100644
index 0000000..02e0231
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
@@ -0,0 +1,52 @@
+QorIQ DPAA Buffer Manager Portals Device Tree Binding
+
+Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
+
+CONTENTS
+
+ - BMan Portal
+ - Example
+
+BMan Portal Node
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,bman-portal-<hardware revision>"
+ May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"
+
+- reg
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Two regions. The first is the cache-enabled region of
+ the portal. The second is the cache-inhibited region of
+ the portal
+
+- interrupts
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Standard property
+
+EXAMPLE
+
+The example below shows a (P4080) BMan portals container/bus node with two portals
+
+ bman-portals@ff4000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0xf 0xf4000000 0x200000>;
+
+ bman-portal@0 {
+ compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
+ reg = <0x0 0x4000>, <0x100000 0x1000>;
+ interrupts = <105 2 0 0>;
+ };
+ bman-portal@4000 {
+ compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
+ reg = <0x4000 0x4000>, <0x101000 0x1000>;
+ interrupts = <107 2 0 0>;
+ };
+ };
--
2.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)
2014-10-28 9:15 ` [PATCH v2 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s) Emil Medve
@ 2014-10-28 14:41 ` Kumar Gala
[not found] ` <044D58B4-690A-4CEA-B2DB-8AF4549D4AE2__43711.2007676207$1414507333$gmane$org@codeaurora.org>
1 sibling, 0 replies; 9+ messages in thread
From: Kumar Gala @ 2014-10-28 14:41 UTC (permalink / raw)
To: Emil Medve
Cc: mark.rutland, devicetree, pawel.moll, ijc+devicetree,
Geoff.Thorpe, corbet, linux-doc, linuxppc-dev, grant.likely,
robh+dt, scottwood
On Oct 28, 2014, at 4:15 AM, Emil Medve <Emilian.Medve@freescale.com> =
wrote:
> Portals are memory mapped interfaces to BMan that allow low-latency,
> lock-less interaction by software running on processor cores, =
accelerators
> and network interfaces with the BMan
>=20
> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
> Change-Id: I6d245ffc14ba3d0e91d403ac7c3b91b75a9e6a95
> ---
> .../bindings/powerpc/fsl/bman-portals.txt | 52 =
++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 =
Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
>=20
> diff --git =
a/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt =
b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
similar comment about location of binding not being PPC specific.
> new file mode 100644
> index 0000000..02e0231
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
> @@ -0,0 +1,52 @@
> +QorIQ DPAA Buffer Manager Portals Device Tree Binding
> +
Probably worth putting the text from the commit message here as well.
> +Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
> +
> +CONTENTS
> +
> + - BMan Portal
> + - Example
> +
> +BMan Portal Node
> +
> +PROPERTIES
> +
> +- compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must include "fsl,bman-portal-<hardware =
revision>"
> + May include "fsl,<SoC>-bman-portal" or =
"fsl,bman-portal"
> +
> +- reg
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: Two regions. The first is the cache-enabled =
region of
> + the portal. The second is the cache-inhibited =
region of
> + the portal
> +
> +- interrupts
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: Standard property
> +
> +EXAMPLE
> +
> +The example below shows a (P4080) BMan portals container/bus node =
with two portals
> +
> + bman-portals@ff4000000 {
> + #address-cells =3D <1>;
> + #size-cells =3D <1>;
> + compatible =3D "simple-bus";
> + ranges =3D <0 0xf 0xf4000000 0x200000>;
> +
> + bman-portal@0 {
> + compatible =3D "fsl,bman-portal-1.0.0", =
"fsl,bman-portal";
> + reg =3D <0x0 0x4000>, <0x100000 0x1000>;
> + interrupts =3D <105 2 0 0>;
> + };
> + bman-portal@4000 {
> + compatible =3D "fsl,bman-portal-1.0.0", =
"fsl,bman-portal";
> + reg =3D <0x4000 0x4000>, <0x101000 0x1000>;
> + interrupts =3D <107 2 0 0>;
> + };
> + };
> --=20
> 2.1.2
>=20
--=20
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora =
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* Re: [PATCH v2 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)
[not found] ` <044D58B4-690A-4CEA-B2DB-8AF4549D4AE2__43711.2007676207$1414507333$gmane$org@codeaurora.org>
@ 2014-10-29 21:26 ` Emil Medve
0 siblings, 0 replies; 9+ messages in thread
From: Emil Medve @ 2014-10-29 21:26 UTC (permalink / raw)
To: Kumar Gala
Cc: mark.rutland, devicetree, pawel.moll, corbet, Geoff.Thorpe,
ijc+devicetree, linux-doc, scottwood, linuxppc-dev, robh+dt,
grant.likely
Hello Kumar,
On 10/28/2014 09:41 AM, Kumar Gala wrote:
> On Oct 28, 2014, at 4:15 AM, Emil Medve <Emilian.Medve@freescale.com> wrote:
>
>> Portals are memory mapped interfaces to BMan that allow low-latency,
>> lock-less interaction by software running on processor cores, accelerators
>> and network interfaces with the BMan
>>
>> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
>> Change-Id: I6d245ffc14ba3d0e91d403ac7c3b91b75a9e6a95
>> ---
>> .../bindings/powerpc/fsl/bman-portals.txt | 52 ++++++++++++++++++++++
>> 1 file changed, 52 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
>>
>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
>
> similar comment about location of binding not being PPC specific.
Will move it to Documentation/devicetree/bindings/soc
>> new file mode 100644
>> index 0000000..02e0231
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
>> @@ -0,0 +1,52 @@
>> +QorIQ DPAA Buffer Manager Portals Device Tree Binding
>> +
>
> Probably worth putting the text from the commit message here as well.
Ok
Cheers,
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan
2014-10-28 9:15 [PATCH v2 0/4] dt/bindings: Introduce the FSL B/QMan Emil Medve
2014-10-28 9:15 ` [PATCH v2 1/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan Emil Medve
2014-10-28 9:15 ` [PATCH v2 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s) Emil Medve
@ 2014-10-28 9:15 ` Emil Medve
2014-10-28 9:15 ` [PATCH v2 4/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s) Emil Medve
3 siblings, 0 replies; 9+ messages in thread
From: Emil Medve @ 2014-10-28 9:15 UTC (permalink / raw)
To: scottwood, galak, corbet, robh+dt, ijc+devicetree, galak,
pawel.moll, mark.rutland, grant.likely, Geoff.Thorpe,
linuxppc-dev, devicetree, linux-doc
Cc: Emil Medve
The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA).
QMan supports queuing and QoS scheduling of frames to CPUs, network interfaces
and DPAA logic modules, maintains packet ordering within flows. Besides
providing flow-level queuing, is also responsible for congestion management
functions such as RED/WRED, congestion notifications and tail discards. This
binding covers the CCSR space programming model
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b
---
.../devicetree/bindings/powerpc/fsl/qman.txt | 133 +++++++++++++++++++++
1 file changed, 133 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/qman.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/qman.txt b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
new file mode 100644
index 0000000..a21e097
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
@@ -0,0 +1,133 @@
+QorIQ DPAA Queue Manager Device Tree Binding
+
+Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
+
+CONTENTS
+
+ - QMan Node
+ - QMan Private Memory Nodes
+ - Example
+
+QMan Node
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,qman"
+ May include "fsl,<SoC>-qman"
+
+- reg
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Registers region within the CCSR address space
+
+- interrupts
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Standard property. The error interrupt
+
+- fsl,liodn
+ Usage: See pamu.txt
+ Value type: <prop-encoded-array>
+ Definition: PAMU property used for static LIODN assignment
+
+- fsl,iommu-parent
+ Usage: See pamu.txt
+ Value type: <phandle>
+ Definition: PAMU property used for dynamic LIODN assignment
+
+ For additional details about the PAMU/LIODN binding(s) see pamu.txt
+
+- clocks
+ Usage: See clock-bindings.txt and qoriq-clock.txt
+ Value type: <prop-encoded-array>
+ Definition: Reference input clock. Its frequency is half of the
+ platform clock
+
+QMan Private Memory Nodes
+
+QMan requires two contiguous range of physical memory used for the backing store
+for QMan Frame Queue Descriptor and Packed Frame Descriptor Record. This memory
+is reserved/allocated as a nodes under the /reserved-memory node
+
+The QMan FQD memory node must be named "qman-fqd"
+
+PROPERTIES
+
+- compatible
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must inclide "fsl,qman-fqd"
+
+The QMan PFDR memory node must be named "qman-pfdr"
+
+PROPERTIES
+
+- compatible
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must inclide "fsl,qman-pfdr"
+
+The following constraints are relevant to the FQD and PFDR private memory:
+ - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
+ 1 GiB
+ - The alignment must be a muliptle of the memory size
+
+The size of the FQD and PFDP must be chosen by observing the hardware features
+configured via the RCW and that are relevant to a specific board (e.g. number of
+MAC(s) pinned-out, number of offline/host command FMan ports, etc.). The size
+configured in the DT must reflect the hardware capabilities and not the specific
+needs of an application
+
+For additional details about reserved memory regions see reserved-memory.txt
+
+EXAMPLE
+
+The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ qman-fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0xf 0xffffffff>;
+ size = <0 0x400000>;
+ alignment = <0 0x400000>;
+ };
+ qman-pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0xf 0xffffffff>;
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ };
+ };
+
+The example below shows a (P4080) QMan CCSR-space node
+
+ clockgen: global-utilities@e1000 {
+ ...
+ sysclk: sysclk {
+ ...
+ };
+ ...
+ platform_pll: platform-pll@c00 {
+ #clock-cells = <1>;
+ reg = <0xc00 0x4>;
+ compatible = "fsl,qoriq-platform-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "platform-pll", "platform-pll-div2";
+ };
+ ...
+ };
+
+ qman@318000 {
+ compatible = "fsl,qman";
+ reg = <0x318000 0x1000>;
+ interrupts = <16 2 1 3>
+ fsl,liodn = <0x16>;
+ clocks = <&platform_pll 1>;
+ };
--
2.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s)
2014-10-28 9:15 [PATCH v2 0/4] dt/bindings: Introduce the FSL B/QMan Emil Medve
` (2 preceding siblings ...)
2014-10-28 9:15 ` [PATCH v2 3/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan Emil Medve
@ 2014-10-28 9:15 ` Emil Medve
3 siblings, 0 replies; 9+ messages in thread
From: Emil Medve @ 2014-10-28 9:15 UTC (permalink / raw)
To: scottwood, galak, corbet, robh+dt, ijc+devicetree, galak,
pawel.moll, mark.rutland, grant.likely, Geoff.Thorpe,
linuxppc-dev, devicetree, linux-doc
Cc: Emil Medve
Portals are memory mapped interfaces to QMan that allow low-latency,
lock-less interaction by software running on processor cores,
accelerators and network interfaces with the QMan
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I29764fa8093b5ce65460abc879446795c50d7185
---
.../bindings/powerpc/fsl/qman-portals.txt | 151 +++++++++++++++++++++
1 file changed, 151 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt
new file mode 100644
index 0000000..86b06d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt
@@ -0,0 +1,151 @@
+QorIQ DPAA Queue Manager Portals Device Tree Binding
+
+Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
+
+CONTENTS
+
+ - QMan Portal
+ - QMan Pool Channel
+ - Example
+
+QMan Portal Node
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,qman-portal-<hardware revision>"
+ May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"
+
+- reg
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Two regions. The first is the cache-enabled region of
+ the portal. The second is the cache-inhibited region of
+ the portal
+
+- interrupts
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Standard property
+
+- fsl,liodn
+ Usage: See pamu.txt
+ Value type: <prop-encoded-array>
+ Definition: PAMU property used for static LIODN assignment
+
+- fsl,iommu-parent
+ Usage: See pamu.txt
+ Value type: <phandle>
+ Definition: PAMU property used for dynamic LIODN assignment. This is
+ an optional property. It is a valid configuration for
+ this phandle to be dangling
+
+ For additional details about the PAMU/LIODN binding(s) see pamu.txt
+
+- fsl,qman-channel-id
+ Usage: Required
+ Value type: <u32>
+ Definition: The hardware index of the channel. This can also be
+ determined by dividing any of the channel's 8 work queue
+ IDs by 8
+
+In addition to these properties the qman-portals should have sub-nodes to
+represent the HW devices/portals that are connected to the software portal
+described here
+
+The currently support sub-nodes are:
+ * fman@0
+ * fman@1
+ * pme@0
+ * crypto@0
+
+These subnodes should have the following properties:
+
+- fsl,liodn
+ Usage: See pamu.txt
+ Value type: <prop-encoded-array>
+ Definition: PAMU property used for static LIODN assignment
+
+- fsl,iommu-parent
+ Usage: See pamu.txt
+ Value type: <phandle>
+ Definition: PAMU property used for dynamic LIODN assignment
+
+- dev-handle
+ Usage: Required
+ Value type: <phandle>
+ Definition: The phandle to the particular hardware device that this
+ portal is connected to.
+
+DPAA QMan Pool Channel Nodes
+
+Pool Channels are defined with the following properties.
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,qman-pool-channel"
+ May include "fsl,<SoC>-qman-pool-channel"
+
+- fsl,qman-channel-id
+ Usage: Required
+ Value type: <u32>
+ Definition: The hardware index of the channel. This can also be
+ determined by dividing any of the channel's 8 work queue
+ IDs by 8
+
+EXAMPLE
+
+The example below shows a (P4080) BMan portals container/bus node with two portals
+
+ qman-portals@ff4200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0xf 0xf4200000 0x200000>;
+
+ qman-portal@0 {
+ compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
+ reg = <0 0x4000>, <0x100000 0x1000>;
+ interrupts = <104 2 0 0>;
+ fsl,liodn = <1 2>;
+ fsl,qman-channel-id = <0>;
+
+ fman@0 {
+ fsl,liodn = <0x21>;
+ dev-handle = <&fman0>;
+ };
+ fman@1 {
+ fsl,liodn = <0xa1>;
+ dev-handle = <&fman1>;
+ };
+ crypto@0 {
+ fsl,liodn = <0x41 0x66>;
+ dev-handle = <&crypto>;
+ };
+ };
+ qman-portal@4000 {
+ compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
+ reg = <0x4000 0x4000>, <0x101000 0x1000>;
+ interrupts = <106 2 0 0>;
+ fsl,liodn = <3 4>;
+ fsl,qman-channel-id = <1>;
+
+ fman@1 {
+ fsl,liodn = <0xa2>;
+ dev-handle = <&fman0>;
+ };
+ fman@0 {
+ fsl,liodn = <0x22>;
+ dev-handle = <&fman1>;
+ };
+ crypto@0 {
+ fsl,liodn = <0x42 0x67>;
+ dev-handle = <&crypto>;
+ };
+ };
+ };
--
2.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread